Message-Id: <200302111906.h1BJ6gU6006172@turing-police.cc.vt.edu>
To: dank@suburbanjihad.net (nick black)
Cc: linux-kernel@vger.kernel.org
Subject: Re: checksumming with mmx, comment in arch/i386/lib/mmx.c 
In-Reply-To: Your message of "Tue, 11 Feb 2003 13:37:07 EST."
             <20030211183707.GA23376@suburbanjihad.net> 
From: Valdis.Kletnieks@vt.edu
References: <20030211183707.GA23376@suburbanjihad.net>
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Date: Tue, 11 Feb 2003 14:06:42 -0500
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On Tue, 11 Feb 2003 13:37:07 EST, dank@suburbanjihad.net (nick black)  said:

> firstly, to what domain of checksums does this comment apply?  secondly,
> why is it true?  it seems the PADDW family of instructions could work
> well here; is the slowdown a result of the kernel's need to muck with
> fpu state (from what i can tell, mmx uses the fp registers)?

(Note - second-hand info from somebody else who looked at MMX/SSE to optimize
an inner loop.  Double-check with CPU documentation).

There's a big "urp" sound as the processor switches from FP to MMX mode and
back, which apparently takes a large number of cycles.  You can to some extent
amortize this if you're switching once for a LONG loop (the analysis I saw was
with a million or so pixels on a screen image) - if you're switching in and out
for a 1500 byte packet (or even worse, a 100-byte packet) the impact may be
more noticable. You may wish to examine the SSE/SSE2 opcodes, which apparently
don't take this performance hit.

-- 
				Valdis Kletnieks
				Computer Systems Senior Engineer
				Virginia Tech


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