Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752347AbbGQQLi (ORCPT ); Fri, 17 Jul 2015 12:11:38 -0400 Received: from mail-bl2on0084.outbound.protection.outlook.com ([65.55.169.84]:62325 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752125AbbGQQLb (ORCPT ); Fri, 17 Jul 2015 12:11:31 -0400 X-Greylist: delayed 906 seconds by postgrey-1.27 at vger.kernel.org; Fri, 17 Jul 2015 12:11:29 EDT Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; vger.kernel.org; dkim=none (message not signed) header.d=none; Authentication-Results: linuxfoundation.org; dkim=none (message not signed) header.d=none; From: To: , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Petr Cvek , , , , Alan Tull Subject: [PATCH v9 2/7] staging: usage documentation for simple fpga bus Date: Fri, 17 Jul 2015 10:51:12 -0500 Message-ID: <1437148277-5405-3-git-send-email-atull@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> References: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: DM2PR21CA0039.namprd21.prod.outlook.com (25.161.137.177) To CY1PR03MB1519.namprd03.prod.outlook.com (25.163.17.25) X-Microsoft-Exchange-Diagnostics-untrusted: 1;CY1PR03MB1519;2:NgDlVafamkjSrh2ZG5syiJh4OBf1ZSSkV4t856vTr2qI/uc0zSCSSD/kTwPuH757;3:AAJE6qBActb/pgKaHunoqoLzlE+vpKutUFZB9rOCqtA93pHftr0LVprzrlXxB3wMHQAznPZ0IDUI08d0gemiQCnHtCB0042dI+jOrFmg2thXZ5KftaQOUsAGFmgS1ix1oDHnGwMJBOgtdlPLcofARw==;25:Mns4CEAJ2VQABzrctiN3Xg+a6J521r07i3UQ0xOYGxN3912HBp22cFiBsszLPzlFbnT4mQz5NzZyQnc3P5qAKdtsw6Sgf9tfqEv20E0zf+pl2JlE21NnRbDGgiAB9RyVD1ZA24lNkypo2ecnTyXpAwumRot6gfNgiA283z1cHxbHdjNivohgW0Ly/g2OaifW/A5MdZjHcccZQEKj1Me/aaWoDtmMTtW1NsiX10eO7stpvF6No2KksjVBiVvNwTZ8X7bg3b0lu5j2uJ5lmq7H9g==;20:/jK8MRX9ayNRz/zY7MFD+Z9AkfHbY+yitZ/YBI6u5t7oJXqhwM04YGEobl7ygleDOk96qGGqH025NT14QZHcU5h6WxMdYqtVRbE0DfuY1jcw79K6fa5KYOFyqgfxA6xZ5etrR9l9QgIUeThlKC77SpJNrrREcaufGw/CPFBY4Wc= X-Microsoft-Antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:CY1PR03MB1519;UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BY2PR03MB128; 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Signed-off-by: Alan Tull --- .../staging/fpga/Documentation/simple-fpga-bus.txt | 48 ++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 drivers/staging/fpga/Documentation/simple-fpga-bus.txt diff --git a/drivers/staging/fpga/Documentation/simple-fpga-bus.txt b/drivers/staging/fpga/Documentation/simple-fpga-bus.txt new file mode 100644 index 0000000..9df519f --- /dev/null +++ b/drivers/staging/fpga/Documentation/simple-fpga-bus.txt @@ -0,0 +1,48 @@ + Simple FPGA Bus + + Alan Tull 2015 + + Overview + -------- +The simple FPGA bus adds device tree overlay support for FPGA's. Loading a +DT overlay will result in the FGPA getting an image loaded, its bridges will +be released, and the DT populated for nodes below the simple-fpga-bus. This +results in drivers getting probed for the hardware that just got added. This +is intended to support the FPGA usage where the FPGA has hardware that +requires drivers. Removing the overlay will result in the drivers getting +removed and the bridges being disabled. + + + Requirements + ------------ + 1. An FPGA image that has a hardware block or blocks that use drivers that are + supported in the kernel. + 2. A device tree overlay. + 3. A FPGA manager driver supporting writing the FPGA. + 4. FPGA bridge resets supported as reset controllers. + +The DT overlay includes bindings (documented in bindings/simple-fpga-bus.txt) +that specify: + * Which fpga manager to use + * Which image file to load + * Flags indicating whether this this image is for full reconfiguration or + partial. + * a list of resets that should be released. These enable the FPGA bridges. + * child nodes specifying the devices that will be added with appropriate + compatible strings, etc. + +Since this code uses the firmware interface to get the image and DT overlay, +they currently have to be files on the filesystem. It doesn't have to be that +way forever as DT bindings could be added to point to other sources for the +image. + + + Sequence + -------- + 1. Load the DT overlay. One convenient way to do that is to use Pantelis' + handy configfs interface (more below). + 2. The simple FPGA bus gets probed and will do the following: + a. call the fpga manager core to program the FPGA + b. release the FPGA bridges + c. call of_platform_populate resulting in device drivers getting probed. + -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/