Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755215AbbGQR1G (ORCPT ); Fri, 17 Jul 2015 13:27:06 -0400 Received: from quartz.orcorp.ca ([184.70.90.242]:36516 "EHLO quartz.orcorp.ca" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753783AbbGQR1E (ORCPT ); Fri, 17 Jul 2015 13:27:04 -0400 Date: Fri, 17 Jul 2015 11:25:58 -0600 From: Jason Gunthorpe To: atull@opensource.altera.com Cc: gregkh@linuxfoundation.org, hpa@zytor.com, monstr@monstr.eu, michal.simek@xilinx.com, rdunlap@infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, pantelis.antoniou@konsulko.com, robh+dt@kernel.org, grant.likely@linaro.org, iws@ovro.caltech.edu, linux-doc@vger.kernel.org, pavel@denx.de, broonie@kernel.org, philip@balister.org, rubini@gnudd.com, s.trumtrar@pengutronix.de, jason@lakedaemon.net, kyle.teske@ni.com, nico@linaro.org, balbi@ti.com, m.chehab@samsung.com, davidb@codeaurora.org, rob@landley.net, davem@davemloft.net, cesarb@cesarb.net, sameo@linux.intel.com, akpm@linux-foundation.org, linus.walleij@linaro.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devel@driverdev.osuosl.org, Petr Cvek , delicious.quinoa@gmail.com, dinguyen@opensource.altera.com, yvanderv@opensource.altera.com Subject: Re: [PATCH v9 0/7] FPGA Manager Framework and Simple FPGA Bus Message-ID: <20150717172558.GB15808@obsidianresearch.com> References: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-Broken-Reverse-DNS: no host name found for IP address 10.0.0.192 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 902 Lines: 21 On Fri, Jul 17, 2015 at 10:51:10AM -0500, atull@opensource.altera.com wrote: > From: Alan Tull > > This patchset adds two chunks plus documentation: > * fpga manager core: exports ABI functions that write an image to a FPGA > * DT Overlay support: simple-fpga-bus to handle FPGA from a DT overlay I didn't read super closely, but overall it makes sense to me.. Providing an in-kernel API will let someone else figure out how to expose that to user space. The DT based scheme seems pretty nice. Can you use this without DT overlay? Ie if I provide the FGPA description as part of my boot time DT will it just work? Jason -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/