Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753060AbbGQTr6 (ORCPT ); Fri, 17 Jul 2015 15:47:58 -0400 Received: from mail-wi0-f173.google.com ([209.85.212.173]:35763 "EHLO mail-wi0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751900AbbGQTr4 (ORCPT ); Fri, 17 Jul 2015 15:47:56 -0400 MIME-Version: 1.0 In-Reply-To: <1435612935-24425-3-git-send-email-andi@firstfloor.org> References: <1435612935-24425-1-git-send-email-andi@firstfloor.org> <1435612935-24425-3-git-send-email-andi@firstfloor.org> Date: Fri, 17 Jul 2015 12:47:55 -0700 Message-ID: Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake From: Stephane Eranian To: Andi Kleen Cc: Peter Zijlstra , LKML , Andi Kleen Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4165 Lines: 103 On Mon, Jun 29, 2015 at 2:22 PM, Andi Kleen wrote: > From: Andi Kleen > > Skylake has a new FRONTEND_LATENCY PEBS event to accurate profile > frontend problems (like ITLB or decoding issues) > > The new event is configured through a separate MSR, which selects > a range of sub events. > > Define the extra MSR as a extra reg and export support for it > through sysfs. To avoid duplicating the existing > tables use a new function to add new entries to existing tables. > > Signed-off-by: Andi Kleen > --- > arch/x86/include/asm/msr-index.h | 2 ++ > arch/x86/kernel/cpu/perf_event.h | 1 + > arch/x86/kernel/cpu/perf_event_intel.c | 11 ++++++++++- > 3 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 96a00de..a5371dc 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -133,6 +133,8 @@ > #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) > #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) > > +#define MSR_PEBS_FRONTEND 0x000003f7 > + > #define MSR_IA32_POWER_CTL 0x000001fc > > #define MSR_IA32_MC0_CTL 0x00000400 > diff --git a/arch/x86/kernel/cpu/perf_event.h b/arch/x86/kernel/cpu/perf_event.h > index 2a4701c..6bd7390 100644 > --- a/arch/x86/kernel/cpu/perf_event.h > +++ b/arch/x86/kernel/cpu/perf_event.h > @@ -47,6 +47,7 @@ enum extra_reg_type { > EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */ > EXTRA_REG_LBR = 2, /* lbr_select */ > EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */ > + EXTRA_REG_FE = 4, /* fe_* */ > > EXTRA_REG_MAX /* number of entries needed */ > }; > diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c > index 4df6783..c6cac61 100644 > --- a/arch/x86/kernel/cpu/perf_event_intel.c > +++ b/arch/x86/kernel/cpu/perf_event_intel.c > @@ -205,6 +205,7 @@ static struct extra_reg intel_skl_extra_regs[] __read_mostly = { > INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0), > INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1), > INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd), > + INTEL_UEVENT_EXTRA_REG_TVAL(0x01c6, MSR_PEBS_FRONTEND, 0x3fff17, FE, 0x11UL), I believe this mask of 0x3fff17 is wrong and should instead be 0x7fffff based on the description of the FRONTEND MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some valid latency values may be rejected. > EVENT_EXTRA_END > }; > > @@ -2875,6 +2876,8 @@ PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63"); > > PMU_FORMAT_ATTR(ldlat, "config1:0-15"); > > +PMU_FORMAT_ATTR(frontend, "config1:0-23"); > + > static struct attribute *intel_arch3_formats_attr[] = { > &format_attr_event.attr, > &format_attr_umask.attr, > @@ -2891,6 +2894,11 @@ static struct attribute *intel_arch3_formats_attr[] = { > NULL, > }; > > +static struct attribute *skl_format_attr[] = { > + &format_attr_frontend.attr, > + NULL, > +}; > + > static __initconst const struct x86_pmu core_pmu = { > .name = "core", > .handle_irq = x86_pmu_handle_irq, > @@ -3500,7 +3508,8 @@ __init int intel_pmu_init(void) > > x86_pmu.hw_config = hsw_hw_config; > x86_pmu.get_event_constraints = hsw_get_event_constraints; > - x86_pmu.cpu_events = hsw_events_attrs; > + x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr, > + skl_format_attr); > WARN_ON(!x86_pmu.format_attrs); > x86_pmu.cpu_events = hsw_events_attrs; > pr_cont("Skylake events, "); > -- > 2.4.2 > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/