Date: Fri, 17 Jul 2015 13:33:15 -0700
From: Andi Kleen <ak@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Stephane Eranian <eranian@google.com>, Andi Kleen <andi@firstfloor.org>,
        Peter Zijlstra <peterz@infradead.org>,
        LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake
Message-ID: <20150717203315.GI7380@tassilo.jf.intel.com>
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On Fri, Jul 17, 2015 at 10:11:28PM +0200, Thomas Gleixner wrote:
> On Fri, 17 Jul 2015, Andi Kleen wrote:
> 
> > > I believe this mask of 0x3fff17 is wrong and should instead be
> > > 0x7fffff based on the description of the FRONTEND
> > > MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some
> > > valid latency values may be rejected.
> > 
> > No, my mask is correct.
> 
> Provide a proper argument for that. Just claiming 'my mask is correct'
> definitely falls not into that category.

Because I actually tested the code unlike you or Stephane.

# wrmsr 0x3f7 0x3fff17
# wrmsr 0x3f7 0x7fffff
wrmsr: CPU 0 cannot set MSR 0x000003f7 to 0x00000000007fffff
# 

-Andi

-- 
ak@linux.intel.com -- Speaking for myself only
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