Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754585AbbGQUlJ (ORCPT ); Fri, 17 Jul 2015 16:41:09 -0400 Received: from mail-wi0-f170.google.com ([209.85.212.170]:33390 "EHLO mail-wi0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754522AbbGQUlG (ORCPT ); Fri, 17 Jul 2015 16:41:06 -0400 MIME-Version: 1.0 In-Reply-To: <20150717200900.GE7380@tassilo.jf.intel.com> References: <1435612935-24425-1-git-send-email-andi@firstfloor.org> <1435612935-24425-3-git-send-email-andi@firstfloor.org> <20150717200900.GE7380@tassilo.jf.intel.com> Date: Fri, 17 Jul 2015 13:41:04 -0700 Message-ID: Subject: Re: [PATCH 3/3] x86, perf: Add PEBS frontend profiling for Skylake From: Stephane Eranian To: Andi Kleen Cc: Andi Kleen , Peter Zijlstra , LKML Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 995 Lines: 27 Andi, On Fri, Jul 17, 2015 at 1:09 PM, Andi Kleen wrote: >> I believe this mask of 0x3fff17 is wrong and should instead be >> 0x7fffff based on the description of the FRONTEND >> MSR I see in the SDM Table 18-54 (bit 0-22 are valid). Otherwise, some >> valid latency values may be rejected. > > No, my mask is correct. > Ok, so your event mask (0x17) really only allows what's defined instead the full width of the field. As for the IDQ_BUBBLE_WIDTH, you only allow 2 bits out of 3, so maximum bubble threshold is 3 instead of 7. I assume this is because you know that it cannot have more than 3 simultaneously then. Would be good to explain this a bit more in the code. > -- > ak@linux.intel.com -- Speaking for myself only -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/