Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754576AbbGQVrL (ORCPT ); Fri, 17 Jul 2015 17:47:11 -0400 Received: from mail-by2on0087.outbound.protection.outlook.com ([207.46.100.87]:28536 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754072AbbGQVrG (ORCPT ); Fri, 17 Jul 2015 17:47:06 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.227) smtp.mailfrom=opensource.altera.com; infradead.org; dkim=none (message not signed) header.d=none; Authentication-Results: ettus.com; dkim=none (message not signed) header.d=none; Date: Fri, 17 Jul 2015 16:42:16 -0500 From: atull X-X-Sender: atull@linuxheads99 To: Moritz Fischer CC: Greg KH , , , Michal Simek , Michal Simek , , , , , , , , , , , , , , , , , , , , , Philip Balister , Petr Cvek , , , , , , , , Kumar Gala , , , Subject: Re: [PATCH v9 7/7] staging: fpga manager: add driver for socfpga fpga manager In-Reply-To: Message-ID: References: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> <1437148277-5405-8-git-send-email-atull@opensource.altera.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: text/plain; 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I have worked with Michal and developed a > Zynq equivalent against your last > patchset which can be found in the Xilinx tree now. > > I just briefly glanced the changes below just two nits that caught my eye. > I'll take a closer look while trying to update the zynq-fpga driver to > work with your changes. > ... > > +#include > > +#include > > +#include > > +#include > > +#include > As you removed the suspend / resume part, do you still need this? > > +#include Yep, I can take out this include. > > + > > +/* > > + * Prepare the FPGA to receive the configuration data. > > + */ > > +static int socfpga_fpga_ops_configure_init(struct fpga_manager *mgr, u32 flags, > > + const char *buf, size_t count) > Is there a reason buf and count need to be passed here? > > +{ > > + struct socfpga_fpga_priv *priv = mgr->priv; > > + int ret; Its to allow .write_init to look at the image header if it needs to. Not every FPGA manager is going to need buf and count. This one doesn't (cyclone5). Your .write_init can ignore them if you don't need them. But Arria10 does (that's a separate driver that I didn't include in this patchset). In that case I need to parse the image header to know whether the bitstream is compressed, etc. to know how to configure the FPGA manager registers before the FPGA can receive image data. Thanks for reviewing! Alan > > > > _______________________________________________ > > devel mailing list > > devel@linuxdriverproject.org > > http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel > > Overall good job, and thanks for pushing this! > > Cheers, > > Moritz > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/