Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754468AbbGTAXa (ORCPT ); Sun, 19 Jul 2015 20:23:30 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:36204 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754026AbbGTAXY (ORCPT ); Sun, 19 Jul 2015 20:23:24 -0400 X-AuditID: cbfee691-f79ca6d00000456a-cb-55ac3f784a70 Message-id: <55AC3F78.3050108@samsung.com> Date: Mon, 20 Jul 2015 09:23:20 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux i686; rv:17.0) Gecko/20130106 Thunderbird/17.0.2 MIME-version: 1.0 To: Sylwester Nawrocki Cc: Krzysztof Kozlowski , tomasz.figa@gmail.com, mturquette@baylibre.com, sboyd@codeaurora.org, kgene@kernel.org, thomas.ab@samsung.com, =?UTF-8?B?QmFydMWCb21pZWogxbtvxYJuaWVya2lld2ljeg==?= , kyungmin.park@samsung.com, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v6 1/3] clk: samsung: exynos3250: Add cpu clock configuration data and instaniate cpu clock References: <1435797761-3339-1-git-send-email-cw00.choi@samsung.com> <1435797761-3339-2-git-send-email-cw00.choi@samsung.com> In-reply-to: Content-type: text/plain; charset=UTF-8 Content-transfer-encoding: 7bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrNIsWRmVeSWpSXmKPExsWyRsSkQLfSfk2oQdtaZouNM9azWsw/co7V 4vULQ4v+x6+ZLc42vWG32PT4GqvFx557rBaXd81hs5hxfh+TxcVTrhaH37SzWvw4081i0bGM 0WLVrj+MDnwe72+0sntc7utl8tg56y67x6ZVnWwem5fUe/RtWcXo8XmTXAB7FJdNSmpOZllq kb5dAlfGr7WFBc2aFR3H37M2ME6V72Lk5JAQMJE4+eUbI4QtJnHh3nq2LkYuDiGBpYwSy7dd Zepi5AAr6j8eBhGfzihxpucyO4TzgFFi45VlTCDdvAJaEp+m7WYDsVkEVCXONveygthsQPH9 L26AxUUFwiRWTr/CAlEvKPFj8j0wW0RAX2LJqotgNcwC25gl7i0PAbGFBQoldu48CzZfSOAY o8SCec4gNqdAsMT9E6eZIOrVJSbNW8QMYctLbF7zlhnkOAmBTg6JzTPesUMcJCDxbfIhFohv ZCU2HWCG+FhS4uCKGywTGMVmITlpFpKxs5CMXcDIvIpRNLUguaA4Kb3IVK84Mbe4NC9dLzk/ dxMjMI5P/3s2cQfj/QPWhxgFOBiVeHgF/q4OFWJNLCuuzD3EaAp0xURmKdHkfGCyyCuJNzQ2 M7IwNTE1NjK3NFMS59WR/hksJJCeWJKanZpakFoUX1Sak1p8iJGJg1MKGF0GFULVc4U5P9nH L3KM2Crrmb7BODRfRv1Wk7NxuuiWjJmrv0YwVUc5KnpKrjc5cOyhiG3MMZXdyx7MlZwp98Qm Y9YZ0e8+s2LC+i2tQjL75/D0eNuxuS57MsMjq2R2WUC1U6Nn/C3+I3FfVjyKMQuYqZY5de/3 KfvFp/TJKrkstimT2pWsxFKckWioxVxUnAgAZH3/rt4CAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprKKsWRmVeSWpSXmKPExsVy+t9jQd0K+zWhBq3LLC02zljPajH/yDlW i9cvDC36H79mtjjb9IbdYtPja6wWH3vusVpc3jWHzWLG+X1MFhdPuVocftPOavHjTDeLRccy RotVu/4wOvB5vL/Ryu5xua+XyWPnrLvsHptWdbJ5bF5S79G3ZRWjx+dNcgHsUQ2MNhmpiSmp RQqpecn5KZl56bZK3sHxzvGmZgaGuoaWFuZKCnmJuam2Si4+AbpumTlABysplCXmlAKFAhKL i5X07TBNCA1x07WAaYzQ9Q0JgusxMkADCWsYM36tLSxo1qzoOP6etYFxqnwXIweHhICJRP/x sC5GTiBTTOLCvfVsXYxcHEIC0xklzvRcZodwHjBKbLyyjAmkildAS+LTtN1sIDaLgKrE2eZe VhCbDSi+/8UNsLioQJjEyulXWCDqBSV+TL4HZosI6EssWXURrIZZYBuzxL3lISC2sEChxM6d Z8HmCwkcY5RYMM8ZxOYUCJa4f+I0E0S9usSkeYuYIWx5ic1r3jJPYBSYhWTFLCRls5CULWBk XsUomlqQXFCclJ5rqFecmFtcmpeul5yfu4kRnCSeSe1gXNlgcYhRgINRiYdX4O/qUCHWxLLi ytxDjBIczEoivBkia0KFeFMSK6tSi/Lji0pzUosPMZoCQ2Ais5Rocj4wgeWVxBsam5gZWRqZ G1oYGZsrifOezPcJFRJITyxJzU5NLUgtgulj4uCUamAUWbc86MjUoCebmB2LnnesmsW8rNhp 8uUi1te21hcu/AtYUirEVhe343vJJPfkLWutlyyX3vTEfNeflJUVT7lbGM4o1stl9Uevu/f+ Ss7HQ8cYtpes/2W3Lsmd0XzPLlM5rXP/mr4xei2QdPbOdjj95E9v37VM67TcPY+dsxgfXyor fO9pzh2jxFKckWioxVxUnAgALCOXNSgDAAA= DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5374 Lines: 127 Hi Sylwester, Please review this patch. Best Regards, Chanwoo Choi On 07/16/2015 04:46 PM, Krzysztof Kozlowski wrote: > 2015-07-02 9:42 GMT+09:00 Chanwoo Choi : >> This patch add CPU clock configuration data and instantiate the CPU clock type >> for Exynos3250 to support Samsung specific cpu-clock type. >> >> Cc: Sylwester Nawrocki >> Cc: Tomasz Figa >> Signed-off-by: Chanwoo Choi >> Acked-by: Kyungmin Park >> Reviewed-by: Krzysztof Kozlowski >> --- >> drivers/clk/samsung/clk-exynos3250.c | 32 ++++++++++++++++++++++++++++++-- >> include/dt-bindings/clock/exynos3250.h | 1 + > > Sylwester, > > I think this patch also waits for your review or ack. > The patchset is rebased on Bartlomiej's series for Exynos5250 cpufreq > so the easiest way would be to take it through samsung-soc tree. > > Best regards, > Krzysztof > > >> 2 files changed, 31 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c >> index 538de66a759e..378ad5ad3492 100644 >> --- a/drivers/clk/samsung/clk-exynos3250.c >> +++ b/drivers/clk/samsung/clk-exynos3250.c >> @@ -19,6 +19,7 @@ >> #include >> >> #include "clk.h" >> +#include "clk-cpu.h" >> #include "clk-pll.h" >> >> #define SRC_LEFTBUS 0x4200 >> @@ -319,8 +320,10 @@ static struct samsung_mux_clock mux_clks[] __initdata = { >> MUX(CLK_MOUT_MPLL_USER_C, "mout_mpll_user_c", mout_mpll_user_p, >> SRC_CPU, 24, 1), >> MUX(CLK_MOUT_HPM, "mout_hpm", mout_hpm_p, SRC_CPU, 20, 1), >> - MUX(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1), >> - MUX(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1), >> + MUX_F(CLK_MOUT_CORE, "mout_core", mout_core_p, SRC_CPU, 16, 1, >> + CLK_SET_RATE_PARENT, 0), >> + MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1, >> + CLK_SET_RATE_PARENT, 0), >> }; >> >> static struct samsung_div_clock div_clks[] __initdata = { >> @@ -772,6 +775,26 @@ static struct samsung_cmu_info cmu_info __initdata = { >> .nr_clk_regs = ARRAY_SIZE(exynos3250_cmu_clk_regs), >> }; >> >> +#define E3250_CPU_DIV0(apll, pclk_dbg, atb, corem) \ >> + (((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \ >> + ((corem) << 4)) >> +#define E3250_CPU_DIV1(hpm, copy) \ >> + (((hpm) << 4) | ((copy) << 0)) >> + >> +static const struct exynos_cpuclk_cfg_data e3250_armclk_d[] __initconst = { >> + { 1000000, E3250_CPU_DIV0(1, 7, 4, 1), E3250_CPU_DIV1(7, 7), }, >> + { 900000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 800000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 700000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 600000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 500000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 400000, E3250_CPU_DIV0(1, 7, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 300000, E3250_CPU_DIV0(1, 5, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 200000, E3250_CPU_DIV0(1, 3, 3, 1), E3250_CPU_DIV1(7, 7), }, >> + { 100000, E3250_CPU_DIV0(1, 1, 1, 1), E3250_CPU_DIV1(7, 7), }, >> + { 0 }, >> +}; >> + >> static void __init exynos3250_cmu_init(struct device_node *np) >> { >> struct samsung_clk_provider *ctx; >> @@ -780,6 +803,11 @@ static void __init exynos3250_cmu_init(struct device_node *np) >> if (!ctx) >> return; >> >> + exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk", >> + mout_core_p[0], mout_core_p[1], 0x14200, >> + e3250_armclk_d, ARRAY_SIZE(e3250_armclk_d), >> + CLK_CPU_HAS_DIV1); >> + >> exynos3_core_down_clock(ctx->reg_base); >> } >> CLK_OF_DECLARE(exynos3250_cmu, "samsung,exynos3250-cmu", exynos3250_cmu_init); >> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h >> index aab088d30199..63d01c15d2b3 100644 >> --- a/include/dt-bindings/clock/exynos3250.h >> +++ b/include/dt-bindings/clock/exynos3250.h >> @@ -31,6 +31,7 @@ >> #define CLK_FOUT_VPLL 4 >> #define CLK_FOUT_UPLL 5 >> #define CLK_FOUT_MPLL 6 >> +#define CLK_ARM_CLK 7 >> >> /* Muxes */ >> #define CLK_MOUT_MPLL_USER_L 16 >> -- >> 1.8.5.5 >> >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > -- > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/