From: Badola Nikhil <nikhil.badola@freescale.com>
To: Mark Rutland <mark.rutland@arm.com>
CC: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "balbi@ti.com" <balbi@ti.com>
Subject: RE: [PATCH 1/3] Documentation: dt: dwc3: Add snps,configure-fladj
 property
Thread-Topic: [PATCH 1/3] Documentation: dt: dwc3: Add snps,configure-fladj
 property
Thread-Index: AQHQxSwX6I6RwEFjPk+QSaNMsW8cdJ3o0V+AgAAByoA=
Date: Thu, 23 Jul 2015 10:52:19 +0000
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References: <1437646161-1764-1-git-send-email-nikhil.badola@freescale.com>
 <20150723095635.GA12330@leverpostej>
In-Reply-To: <20150723095635.GA12330@leverpostej>
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> -----Original Message-----
> From: Mark Rutland [mailto:mark.rutland@arm.com]
> Sent: Thursday, July 23, 2015 3:27 PM
> To: Badola Nikhil-B46172
> Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; balbi@ti.com
> Subject: Re: [PATCH 1/3] Documentation: dt: dwc3: Add snps,configure-fladj
> property
> 
> On Thu, Jul 23, 2015 at 11:09:21AM +0100, Nikhil Badola wrote:
> > Add property snps,configure-fladj for enabling post silicon frame
> > length adjustment
> >
> > Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
> > ---
> >  Documentation/devicetree/bindings/usb/dwc3.txt | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt
> > index 0815eac..90c3972 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > @@ -40,6 +40,7 @@ Optional properties:
> >   - snps,hird-threshold: HIRD threshold
> >   - snps,hsphy_interface: High-Speed PHY interface selection between
> "utmi" for
> >     UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has
> value 3.
> > + - snps,configure-fladj: enables post-silicon frame length adjustment
> 
> Could you elaborate on what this means and why you think it's necessary?

This property enables the use of GFLADJ_30MHZ field value of gfladj register for frame length 
adjustment instead of considering from the sideband input signal fladj_30mhz_reg from SOC. 
This is required when signal fladj_30mhz_reg is connected to a wrong value or is not valid as 
in our case, hence post-silicon.

However this field can be used to adjust any offset ranging from 00h to 3Fh, from the
clock source generating SOF(start of frame) packets. Thus, this property can be added to device 
tree with appropriate adjustment value.

> 
> >
> >  This is usually a subnode to DWC3 glue to which it is connected.
> >
> > --
> > 2.1.0
> >
> > --
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> >
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