Message-ID: <1437665929.3214.313.camel@hp.com>
Subject: Re: [PATCH] x86, pat: Add comments to cachemode translation tables
From: Toshi Kani <toshi.kani@hp.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: peterz@infradead.org, mingo@kernel.org, x86@kernel.org, tglx@linutronix.de,
        bp@suse.de, linux-kernel@vger.kernel.org
Date: Thu, 23 Jul 2015 09:38:49 -0600
In-Reply-To: <55B126070200007800094BD5@prv-mh.provo.novell.com>
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On Thu, 2015-07-23 at 09:36 -0600, Jan Beulich wrote:
> > 
> > > > On 23.07.15 at 17:25, <toshi.kani@hp.com> wrote:
> > Yes, I agree with you.  But such risk is very low -- 1) the regular 
> > case
> > (no fallback) is used most of the cases, 2) the code using WT knows 
> > what
> > type of memory it is dealing with.  For example, pmem may map NVDIMM 
> > with
> > WT, and any sane BIOS sets MTRR to WB for NVDIMM. 
> 
> Do the words "sane" and "BIOS" really fit together in your opinion?

:-)

Anyway, I am not disagreeing with you... When UC is ready for both regular
memory and IO memory, it should be changed to fall back to UC.

Thanks,
-Toshi
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