Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753819AbbGWPwp (ORCPT ); Thu, 23 Jul 2015 11:52:45 -0400 Received: from mail-wi0-f174.google.com ([209.85.212.174]:38696 "EHLO mail-wi0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753406AbbGWPwh (ORCPT ); Thu, 23 Jul 2015 11:52:37 -0400 Date: Thu, 23 Jul 2015 16:52:33 +0100 From: Lee Jones To: Vaibhav Hiremath Cc: linux-arm-kernel@lists.infradead.org, robh+dt@kernel.org, mturquette@baylibre.com, k.kozlowski@samsung.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCH 1/4] mfd: 88pm800: Update the header file with 32K clk related macros Message-ID: <20150723155233.GT3436@x1> References: <1437476823-3358-1-git-send-email-vaibhav.hiremath@linaro.org> <1437476823-3358-2-git-send-email-vaibhav.hiremath@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1437476823-3358-2-git-send-email-vaibhav.hiremath@linaro.org> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2019 Lines: 61 On Tue, 21 Jul 2015, Vaibhav Hiremath wrote: > Update header file with required macros for 32KHz buffered clock > output of 88PM800 family of device. > These macros will be used in clk provider driver. > > Signed-off-by: Vaibhav Hiremath > --- > include/linux/mfd/88pm80x.h | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h > index 05d9bad..680e4eb 100644 > --- a/include/linux/mfd/88pm80x.h > +++ b/include/linux/mfd/88pm80x.h > @@ -91,6 +91,7 @@ enum { > /* Referance and low power registers */ > #define PM800_LOW_POWER1 (0x20) > #define PM800_LOW_POWER2 (0x21) > +#define PM800_LOW_POWER2_XO_LJ_EN BIT(5) > > #define PM800_LOW_POWER_CONFIG3 (0x22) > #define PM800_LDOBK_FREEZE BIT(7) > @@ -138,6 +139,13 @@ enum { > #define PM800_ALARM BIT(5) > #define PM800_RTC1_USE_XO BIT(7) > > +#define PM800_32K_OUTX_SEL_MASK (0x3) > +/* 32KHz clk output sel mode */ > +#define PM800_32K_OUTX_SEL_ZERO (0x0) > +#define PM800_32K_OUTX_SEL_INT_32KHZ (0x1) > +#define PM800_32K_OUTX_SEL_XO_32KHZ (0x2) > +#define PM800_32K_OUTX_SEL_HIZ (0x3) Why do these need to be in brackets? > /* Regulator Control Registers: BUCK1,BUCK5,LDO1 have DVC */ > > /* buck registers */ > @@ -208,6 +216,10 @@ enum { > #define PM800_PMOD_MEAS1 0x52 > #define PM800_PMOD_MEAS2 0x53 > > +/* Oscillator control */ > +#define PM800_OSC_CNTRL1 (0x50) > +#define PM800_OSC_CNTRL1_OSC_FREERUN_EN BIT(1) > + > #define PM800_GPADC0_MEAS1 0x54 > #define PM800_GPADC0_MEAS2 0x55 > #define PM800_GPADC1_MEAS1 0x56 -- Lee Jones Linaro STMicroelectronics Landing Team Lead Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/