Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753630AbbGXDrK (ORCPT ); Thu, 23 Jul 2015 23:47:10 -0400 Received: from mail-bl2on0093.outbound.protection.outlook.com ([65.55.169.93]:54510 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752432AbbGXDrH (ORCPT ); Thu, 23 Jul 2015 23:47:07 -0400 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; infradead.org; dkim=none (message not signed) header.d=none; Authentication-Results: obsidianresearch.com; dkim=none (message not signed) header.d=none; Date: Thu, 23 Jul 2015 22:42:05 -0500 From: atull X-X-Sender: atull@linuxheads99 To: Jason Gunthorpe CC: Moritz Fischer , Greg KH , , Michal Simek , Michal Simek , , , , , Pantelis Antoniou , , , , Nicolas Pitre , , , Grant Likely , David Brown , Linus Walleij , , , , , , , Philip Balister , Petr Cvek , , , , , Alan Tull , , Rob Landley , Kumar Gala , , , Subject: Re: [PATCH v9 6/7] staging: add simple-fpga-bus In-Reply-To: <20150723221510.GA16971@obsidianresearch.com> Message-ID: References: <1437148277-5405-1-git-send-email-atull@opensource.altera.com> <1437148277-5405-7-git-send-email-atull@opensource.altera.com> <20150723221510.GA16971@obsidianresearch.com> User-Agent: Alpine 2.02 (DEB 1266 2009-07-14) MIME-Version: 1.0 Content-Type: text/plain; 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FPGA specific code > has to run around and ensure all DMA is shut off, then we need to make > sure no CPU issued AXI transactions can happen, then we can tear down > the FPGA side. > > If the FPGA is torn down while an AXI op is inprogress things go > sideways, we have to work to prevent that :) > > This happens almost for free, I use DT and the device model to > disconnect the drivers. The drivers are careful to synchronously fence > off in-progress DMA. Then drop the DT nodes associated with the > FPGA, finally the actual FPGA cells can be reset. Yes, the kernel gives us this almost for free. That's what I like about using DT overlays to control FPGA programming. > > > In a partial reconfiguration situation, would I have separate > > simple-fpga buses for each of the parts that I swap out, each with > > it's own reset and bitfile attached? > > I'd think of partial reconfiguration as another nested FPGA. The > resets and so forth could be attached to soft controllers in the > unswappable part of the FPGA. > > DT nodes have to surround it in some way... > > Jason > Yes, in this way each PR chunk will need its own reset so it won't wiggle busses and affect the rest of the system during PR. I noticed that currently simple-fpga-bus.c holds an exclusive ref of the fpga manager. This would keep a 2nd pr from being able to access the same fpga manager, so I'll have to change it so that simple-fpga-bus.c will put the ref before exiting probe. Alan -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/