Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753946AbbGXJAi (ORCPT ); Fri, 24 Jul 2015 05:00:38 -0400 Received: from mail-yk0-f175.google.com ([209.85.160.175]:35104 "EHLO mail-yk0-f175.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753404AbbGXJAe (ORCPT ); Fri, 24 Jul 2015 05:00:34 -0400 MIME-Version: 1.0 In-Reply-To: <8769951.Y5Edyg2WDJ@ubix> References: <1437380237-28961-1-git-send-email-yh.huang@mediatek.com> <1437380237-28961-2-git-send-email-yh.huang@mediatek.com> <8769951.Y5Edyg2WDJ@ubix> From: Daniel Kurtz Date: Fri, 24 Jul 2015 17:00:13 +0800 X-Google-Sender-Auth: t7l-FqZPp5PrF4jdnLC8u8u-TyU Message-ID: Subject: Re: [PATCH v6 1/3] dt-bindings: pwm: add MediaTek display PWM bindings To: Matthias Brugger Cc: YH Huang , Mark Rutland , Thierry Reding , Rob Herring , Pawel Moll , linux-pwm@vger.kernel.org, "open list:OPEN FIRMWARE AND..." , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , srv_heupstream , linux-mediatek@lists.infradead.org, Sascha Hauer , Yingjoe Chen Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2304 Lines: 59 On Fri, Jul 24, 2015 at 4:40 PM, Matthias Brugger wrote: > On Monday, July 20, 2015 04:17:15 PM YH Huang wrote: >> Document the device-tree binding of MediatTek display PWM. >> The PWM has one channel to control the backlight brightness for display. >> It supports MT8173 and MT6595. >> >> Signed-off-by: YH Huang >> --- >> .../devicetree/bindings/pwm/pwm-mtk-disp.txt | 42 >> ++++++++++++++++++++++ 1 file changed, 42 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt >> >> diff --git a/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt >> b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt new file mode >> 100644 >> index 0000000..f8f59ba >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/pwm-mtk-disp.txt >> @@ -0,0 +1,42 @@ >> +MediaTek display PWM controller >> + >> +Required properties: >> + - compatible: should be "mediatek,-disp-pwm": >> + - "mediatek,mt8173-disp-pwm": found on mt8173 SoC. >> + - "mediatek,mt6595-disp-pwm": found on mt6595 SoC. > > I had another look on the mt6589 datasheet and for me it doesn't look like as > if this drivers is compatible to mt6589. Matthias - the compatible is "mt6595", not mt6589 :-). Which datasheet did you check? -Dan > > DISP_PWM_CON_0 offset 0x10 maps to interrupt enable register and > DISP_PWM_CON_1 offset 0x14 maps to interrupt status register. > > This looks wrong to me, as you use both registers to write clock divider and > clock period. > > Regarding that this is v6 of the patch set, I would propose that you just drop > the compatible string for mt6589 or you implement the register offset on basis > of the compatible string so that mt6589 can you the driver as well. > > Best regards, > Matthias > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/