Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755425AbbG0C0Y (ORCPT ); Sun, 26 Jul 2015 22:26:24 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:37446 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755397AbbG0C0X (ORCPT ); Sun, 26 Jul 2015 22:26:23 -0400 Message-ID: <55B59681.2090008@huawei.com> Date: Mon, 27 Jul 2015 10:25:05 +0800 From: "majun (F)" User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: Marc Zyngier , Thomas Gleixner CC: Catalin Marinas , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , "jason@lakedaemon.net" , "lizefan@huawei.com" , "huxinwei@huawei.com" , "dingtianhong@huawei.com" , "zhaojunhua@hisilicon.com" , "liguozhu@hisilicon.com" , "xuwei5@hisilicon.com" , "wei.chenwei@hisilicon.com" , "guohanjun@huawei.com" , "wuyun.wu@huawei.com" , "guodong.xu@linaro.org" , "haojian.zhuang@linaro.org" , "zhangfei.gao@linaro.org" , "usman.ahmad@linaro.org" Subject: Re: [PATCH v3 1/3] IRQ/Gic-V3: Add mbigen driver to support mbigen interrupt controller References: <1436166548-34920-1-git-send-email-majun258@huawei.com> <1436166548-34920-2-git-send-email-majun258@huawei.com> <559CA530.2090508@huawei.com> <559D3EB5.4060408@arm.com> <55A76CBE.2030508@huawei.com> <55A770E2.2040300@arm.com> <55A777BD.4080504@huawei.com> <55A77999.9000203@arm.com> <55A7A2F9.3000306@huawei.com> <55A7B3A5.6010008@arm.com> In-Reply-To: <55A7B3A5.6010008@arm.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.177.236.124] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1523 Lines: 40 Hi Marc 在 2015/7/16 21:37, Marc Zyngier 写道: [...] >> >> For example, An device with total 5 interrupts connected to Mbigen node. >> In mbigen chip, the default eventID value for each device starts from 0. >> So, for these 5 interrupts the default eventID value is from 0 to 4. >> >> Because the default eventID is fixed in mbigen chip, to make these 5 interrupt >> work, the only way is define all these 5 interrupts in dts file. > > But the ITS doesn't read these interrupts, and won't let you program the > translation either. > >> When irq initializing, ITS driver will allocat LPI interrupt number for these >> 5 interrupts, for example : from 8192 to 8196. and the eventID value is from 0 to 4. >> Now, the allocated eventID value same as the eventID value encoded in mbigen chip, >> The interrupt can work. > > But that's pure luck! What if I decide to change the allocation method > so that all the devices share a common ITT? > > Have you really hardcoded the Linux behaviour in your hardware? > >> I know this is not a good method,but for current mbigen chip,it's the only solution. > > I'm sorry, I can't call this a solution. Yes,you are right. This is not a right way to solve the problem. This problem will be fixed in next version chip. > > M. > -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/