Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753112AbbG1EzO (ORCPT ); Tue, 28 Jul 2015 00:55:14 -0400 Received: from mail-lb0-f171.google.com ([209.85.217.171]:35249 "EHLO mail-lb0-f171.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750844AbbG1EzL (ORCPT ); Tue, 28 Jul 2015 00:55:11 -0400 MIME-Version: 1.0 In-Reply-To: <55B5BD08.60802@monstr.eu> References: <1437783682-13632-1-git-send-email-moritz.fischer@ettus.com> <1437783682-13632-2-git-send-email-moritz.fischer@ettus.com> <55B5BD08.60802@monstr.eu> Date: Mon, 27 Jul 2015 21:55:10 -0700 Message-ID: Subject: Re: [RFCv2 1/3] docs: dts: Added documentation for Xilinx Zynq Reset Controller bindings. From: Moritz Fischer To: Michal Simek Cc: p.zabel@pengutronix.de, mark.rutland@arm.com, devicetree@vger.kernel.org, linux@arm.linux.org.uk, pawel.moll@arm.com, ijc+devicetree@hellion.org.uk, Michal Simek , linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-arm-kernel , Kumar Gala , =?UTF-8?Q?S=C3=B6ren_Brinkmann?= Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2494 Lines: 92 Hi Michal, On Sun, Jul 26, 2015 at 10:09 PM, Michal Simek wrote: > On 07/25/2015 02:21 AM, Moritz Fischer wrote: >> Signed-off-by: Moritz Fischer >> --- >> Documentation/devicetree/bindings/reset/zynq-reset-pl.txt | 13 +++++++++++++ >> 1 file changed, 13 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/zynq-reset-pl.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt >> new file mode 100644 >> index 0000000..ac4499e >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/zynq-reset-pl.txt >> @@ -0,0 +1,13 @@ >> +Xilinx Zynq PL Reset Manager > > here > >> + >> +Required properties: >> +- compatible: "xlnx,zynq-reset-pl" > > Currently it is not just PL reset controller. > >> +- syscon <&slcr>; > > > missing : and please be more descriptive here. > >> +- #reset-cells: 1 >> + >> +Example: >> + rstc: rstc@240 { >> + #reset-cells = <1>; >> + compatible = "xlnx,zynq-reset-pl"; > > Compatible property should go first. > > I am missing that reg property > >> + syscon = <&slcr>; >> + }; >> > Would something like this work: Xilinx Zynq Reset Manager The Zynq AP-SoC has several different resets. See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. Required properties: - compatible: "xlnx,zynq-reset" - reg: SLCR offset and size taken via syscon <0x200 0x50> - syscon: <&slcr> This should be a phandle to the Zynq's SLCR register. - #reset-cells: Must be 1 The Zynq Reset Manager needs to be a child node of the SLCR. Example: rstc: rstc@200 { compatible = "xlnx,zynq-reset"; reg = <0x200 0x50>; #reset-cells = <1>; syscon = <&slcr>; }; > Thanks, > Michal > > > -- > Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 > w: www.monstr.eu p: +42-0-721842854 > Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ > Maintainer of Linux kernel - Xilinx Zynq ARM architecture > Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform > > Thanks for your feedback, Moritz -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/