Date: Tue, 28 Jul 2015 18:35:36 +0200
From: Peter Zijlstra <peterz@infradead.org>
To: Vikas Shivappa <vikas.shivappa@linux.intel.com>
Cc: linux-kernel@vger.kernel.org, vikas.shivappa@intel.com, x86@kernel.org,
        hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, tj@kernel.org,
        matt.fleming@intel.com, will.auld@intel.com,
        glenn.p.williamson@intel.com, kanaka.d.juvva@intel.com
Subject: Re: [PATCH 6/9] x86/intel_rdt: Add support for cache bit mask
 management
Message-ID: <20150728163536.GS25159@twins.programming.kicks-ass.net>
References: <1435789270-27010-1-git-send-email-vikas.shivappa@linux.intel.com>
 <1435789270-27010-7-git-send-email-vikas.shivappa@linux.intel.com>
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On Wed, Jul 01, 2015 at 03:21:07PM -0700, Vikas Shivappa wrote:
> +static inline bool cbm_is_contiguous(unsigned long var)
> +{
> +	unsigned long maxcbm = MAX_CBM_LENGTH;
> +	unsigned long first_bit, zero_bit;
> +
> +	if (!var)
> +		return false;
> +
> +	first_bit = find_next_bit(&var, maxcbm, 0);

We actually have: find_first_bit().

> +	zero_bit = find_next_zero_bit(&var, maxcbm, first_bit);
> +
> +	if (find_next_bit(&var, maxcbm, zero_bit) < maxcbm)
> +		return false;
> +
> +	return true;
> +}
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