Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751956AbbG2JIe (ORCPT ); Wed, 29 Jul 2015 05:08:34 -0400 Received: from mail-ob0-f172.google.com ([209.85.214.172]:34473 "EHLO mail-ob0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750836AbbG2JIb (ORCPT ); Wed, 29 Jul 2015 05:08:31 -0400 MIME-Version: 1.0 In-Reply-To: <1438149721-11072-1-git-send-email-leo.yan@linaro.org> References: <1438149721-11072-1-git-send-email-leo.yan@linaro.org> Date: Wed, 29 Jul 2015 11:08:30 +0200 Message-ID: Subject: Re: [rtc-linux] [PATCH] drivers/rtc/rtc-pl031.c: reset registers in init flow From: Linus Walleij To: "rtc-linux@googlegroups.com" Cc: Alessandro Zummo , Alexandre Belloni , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Deepak Saxena , Leo Yan Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1920 Lines: 55 On Wed, Jul 29, 2015 at 8:02 AM, Leo Yan wrote: > When use rtc-pl031 for suspend test on Hisilicon's SoC Hi6220, Usually > the data register (DR) will read back as value zero. So the suspend > test code will set the match register (MR) for 10 seconds' timeout; But > there have chance later will read back some random values from DR > register; So finally miss with match value and will not trigger > waken up event anymore. > > This issue can be dismissed by reset registers in initialization flow; > And this code have no harm for ST's variant. > > Signed-off-by: Leo Yan I don't understand this... > + /* Init registers */ > + writel(0x0, ldata->base + RTC_LR); This will reset the clock to jan 1st 1970 on every reboot. The idea is that the RTC should *preserve* the system time if you reboot the system, so NACK. Usually userspace has a script using hwclock to read the system time from the rtc to system time with hwclock -s after userspace comes up. Likewise it writes it back with hwclock -w before rebooting. > + writel(0x0, ldata->base + RTC_DR); This is a read-only register in the PL031 clean variant. What do you want to achieve here? Is this register writeable on the HiSilicon? > + writel(0x0, ldata->base + RTC_IMSC); OK > + writel(RTC_BIT_AI, ldata->base + RTC_ICR); So why do we want to have the alarm enabled by default, before the kernel nor userspace has requested it? If your problem is with suspend/resume I suggest you work on the [runtime]_suspend/resume hooks instead of probe(). Possibly you need to save/restore state across suspend/resume. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/