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Date: Thu, 30 Jul 2015 09:55:13 +0200
From: Michal Hocko <mhocko@kernel.org>
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	<hidehiro.kawai.ez@hitachi.com>
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	<ltc-kernel@ml.yrl.intra.hitachi.co.jp>,
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	<masami.hiramatsu.pt@hitachi.com>
Subject: Re: Re: [V2 PATCH 1/3] x86/panic: Fix re-entrance problem due to
 panic on NMI
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On Thu 30-07-15 07:33:15, 河合英宏 / KAWAI，HIDEHIRO wrote:
[...]
> Are you using SGI UV?  On that platform, NMIs may be delivered to
> all cpus because LVT1 of all cpus are not masked as follows:

This is Compute Blade 520XB1 from Hitachi with 240 cpus.

-- 
Michal Hocko
SUSE Labs
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