Subject: Re: Dealing with the NMI mess
To: Borislav Petkov <bp@alien8.de>
References: <20150724195509.GM2859@worktop.programming.kicks-ass.net>
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Cc: Andy Lutomirski <luto@amacapital.net>,
        Peter Zijlstra <peterz@infradead.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Willy Tarreau <w@1wt.eu>, Steven Rostedt <rostedt@goodmis.org>,
        X86 ML <x86@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>, Brian Gerst <brgerst@gmail.com>
From: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <55BB4D5A.7070202@redhat.com>
Date: Fri, 31 Jul 2015 12:26:34 +0200
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On 31/07/2015 12:25, Borislav Petkov wrote:
>> > The reason why it isn't documented is probably hidden within Intel.
>> > Besides ICEBP, which is a bit fringe, there's no reason not to document
>> > SALC which Thomas mentioned.  SALC all has been there since the 8086,
>> > and has been undocumented for thirty-odd years.
> That one is invalid (on an IVB):
> 
> [ 1306.231408] traps: icebp[3783] trap invalid opcode ip:4004b0 sp:7fffffffe610 error:0 in icebp[400000+1000]
> 
> AMD APM documents it as invalid too.

It's valid in 32-bit.

Paolo
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