Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751448AbbGaLcZ (ORCPT ); Fri, 31 Jul 2015 07:32:25 -0400 Received: from foss.arm.com ([217.140.101.70]:44694 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750994AbbGaLcX (ORCPT ); Fri, 31 Jul 2015 07:32:23 -0400 Date: Fri, 31 Jul 2015 12:32:17 +0100 From: Will Deacon To: Yong Wu Cc: Mark Rutland , Catalin Marinas , "cloud.chou@mediatek.com" , Joerg Roedel , "frederic.chen@mediatek.com" , "devicetree@vger.kernel.org" , "arnd@arndb.de" , Tomasz Figa , Rob Herring , "linux-mediatek@lists.infradead.org" , Matthias Brugger , "linux-arm-kernel@lists.infradead.org" , "pebolle@tiscali.nl" , Thierry Reding , "srv_heupstream@mediatek.com" , Robin Murphy , "linux-kernel@vger.kernel.org" , "iommu@lists.linux-foundation.org" , Daniel Kurtz , Sasha Hauer , "mitchelh@codeaurora.org" , Lucas Stach , "th.yang@mediatek.com" , "youhua.li@mediatek.com" Subject: Re: [PATCH v3 3/6] iommu: add ARM short descriptor page table allocator. Message-ID: <20150731113217.GE29497@arm.com> References: <1437037475-9065-1-git-send-email-yong.wu@mediatek.com> <1437037475-9065-4-git-send-email-yong.wu@mediatek.com> <20150721171101.GN31095@arm.com> <1437715466.23932.68.camel@mhfsdcap03> <20150724165325.GC21177@arm.com> <1437970868.25925.20.camel@mhfsdcap03> <1438329337.25925.147.camel@mhfsdcap03> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1438329337.25925.147.camel@mhfsdcap03> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1208 Lines: 36 On Fri, Jul 31, 2015 at 08:55:37AM +0100, Yong Wu wrote: > About the AP bits, I may have to add a new quirk for it... > > Current I add AP in pte like this: > #define ARM_SHORT_PTE_RD_WR (3 << 4) > #define ARM_SHORT_PTE_RDONLY BIT(9) > > pteprot |= ARM_SHORT_PTE_RD_WR; > > > If(!(prot & IOMMU_WRITE) && (prot & IOMMU_READ)) > > > pteprot |= ARM_SHORT_PTE_RDONLY; > > The problem is that the BIT(9) in the level1 and level2 pagetable of our > HW has been used for PA[32] that is for the dram size over 4G. Aha, now *thats* a case of page-table abuse! > so I had to add a quirk to disable bit9 while RDONLY case. > (If BIT9 isn't disabled, the HW treat it as the PA[32] case then it will > translation fault..) > > like: IO_PGTABLE_QUIRK_SHORT_MTK ? Given that you don't have XN either, maybe IO_PGTABLE_QUIRK_NO_PERMS? When set, IOMMU_READ/WRITE/EXEC are ignored and the mapping will never generate a permission fault. Will -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/