Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754294AbbGaRGm (ORCPT ); Fri, 31 Jul 2015 13:06:42 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:42352 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752607AbbGaREQ (ORCPT ); Fri, 31 Jul 2015 13:04:16 -0400 From: Stephen Boyd To: Mike Turquette , Stephen Boyd Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Barry Song Subject: [PATCH 19/26] clk: sirf: Convert to clk_hw based provider APIs Date: Fri, 31 Jul 2015 10:03:59 -0700 Message-Id: <1438362246-6664-20-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 2.3.0.rc1.33.g42e4583 In-Reply-To: <1438362246-6664-1-git-send-email-sboyd@codeaurora.org> References: <1438362246-6664-1-git-send-email-sboyd@codeaurora.org> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1990 Lines: 48 We're removing struct clk from the clk provider API, so switch this code to using the clk_hw based provider APIs. Cc: Barry Song Signed-off-by: Stephen Boyd --- drivers/clk/sirf/clk-common.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c index 2f64d4beeb52..77e1e2491689 100644 --- a/drivers/clk/sirf/clk-common.c +++ b/drivers/clk/sirf/clk-common.c @@ -167,10 +167,10 @@ static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate, * SiRF SoC has not cpu clock control, * So bypass to it's parent pll. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - struct clk *pll_parent_clk = clk_get_parent(parent_clk); - unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk); - return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate); + struct clk_hw *parent_clk = clk_hw_get_parent(hw); + struct clk_hw *pll_parent_clk = clk_hw_get_parent(parent_clk); + unsigned long pll_parent_rate = clk_hw_get_rate(pll_parent_clk); + return pll_clk_round_rate(parent_clk, rate, &pll_parent_rate); } static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, @@ -180,8 +180,8 @@ static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw, * SiRF SoC has not cpu clock control, * So return the parent pll rate. */ - struct clk *parent_clk = clk_get_parent(hw->clk); - return __clk_get_rate(parent_clk); + struct clk_hw *parent_clk = clk_hw_get_parent(hw); + return clk_hw_get_rate(parent_clk); } static struct clk_ops std_pll_ops = { -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/