Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751703AbbHBTli (ORCPT ); Sun, 2 Aug 2015 15:41:38 -0400 Received: from www.linutronix.de ([62.245.132.108]:58379 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750972AbbHBTlh (ORCPT ); Sun, 2 Aug 2015 15:41:37 -0400 Date: Sun, 2 Aug 2015 21:41:08 +0200 (CEST) From: Thomas Gleixner To: Shaohua Li cc: x86@kernel.org, linux-kernel@vger.kernel.org, Kernel-team@fb.com, Suresh Siddha , "H. Peter Anvin" , Ingo Molnar , stable@vger.kernel.org Subject: Re: [PATCH] x86: serialize LVTT and TSC_DEADLINE write In-Reply-To: <20150802154948.GA1432307@devbig257.prn2.facebook.com> Message-ID: References: <75ed9226b028a31e37861fbba51cdffbcfe04eda.1438300532.git.shli@fb.com> <20150802154948.GA1432307@devbig257.prn2.facebook.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="8323329-347381284-1438544469=:3825" X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2467 Lines: 67 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-347381284-1438544469=:3825 Content-Type: TEXT/PLAIN; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Sun, 2 Aug 2015, Shaohua Li wrote: > On Sat, Aug 01, 2015 at 12:10:41PM +0200, Thomas Gleixner wrote: > > On Fri, 31 Jul 2015, Shaohua Li wrote: > > > @@ -336,6 +336,22 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) > > > apic_write(APIC_LVTT, lvtt_value); > > > > > > if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { > > > + u64 msr; > > > + > > > + /* > > > + * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, > > > + * writing APIC LVTT and TSC_DEADLINE MSR isn't serialized. > > > + * This uses the algorithm described in Intel SDM to serialize > > > + * the two writes > > > + * */ > > > + while (1) { > > > + wrmsrl(MSR_IA32_TSC_DEADLINE, -1L); > > > + rdmsrl(MSR_IA32_TSC_DEADLINE, msr); > > > + if (msr) > > > + break; > > > + } > > > + wrmsrl(MSR_IA32_TSC_DEADLINE, 0); > > > > > > I think this is exceptionally silly. A proper fence after the > > apic_write() should have the same effect. > > Not sure what happens in the hardware, I could have a try of fence, but > I'd prefer using the algorithm Intel described. This is not a fast path, s/algorithm/voodoo/ > the loop will exit immediately regardless the issue occurs anyway. Well, the SDM also says: "To allow for efficient access to the APIC registers in x2APIC mode, the serializing semantics of WRMSR are relaxed when writing to the APIC registers. Thus, system software should not use “WRMSR to APIC registers in x2APIC mode” as a serializing instruction. Read and write accesses to the APIC registers will occur in program order. A WRMSR to an APIC register may complete before all preceding stores are globally visible; software can prevent this by inserting a serializing instruction, an SFENCE, or an MFENCE before the WRMSR." And that's what happens here. The write to the LVT has not yet hit the APIC, so the WRMSR has no effect. Thanks, tglx --8323329-347381284-1438544469=:3825-- -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/