Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932826AbbHDI6a (ORCPT ); Tue, 4 Aug 2015 04:58:30 -0400 Received: from terminus.zytor.com ([198.137.202.10]:50190 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932331AbbHDI60 (ORCPT ); Tue, 4 Aug 2015 04:58:26 -0400 Date: Tue, 4 Aug 2015 01:57:57 -0700 From: tip-bot for Andi Kleen Message-ID: Cc: ak@linux.intel.com, peterz@infradead.org, tglx@linutronix.de, mingo@kernel.org, hpa@zytor.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org Reply-To: mingo@kernel.org, ak@linux.intel.com, tglx@linutronix.de, peterz@infradead.org, torvalds@linux-foundation.org, hpa@zytor.com, linux-kernel@vger.kernel.org In-Reply-To: <1431285767-27027-8-git-send-email-andi@firstfloor.org> References: <1431285767-27027-8-git-send-email-andi@firstfloor.org> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel: Handle new arch perfmon v4 status bits Git-Commit-ID: d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2372 Lines: 65 Commit-ID: d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f Gitweb: http://git.kernel.org/tip/d8020bee1d0caa90e7b9d6f39ac1fdfaaee7f67f Author: Andi Kleen AuthorDate: Sun, 10 May 2015 12:22:45 -0700 Committer: Ingo Molnar CommitDate: Tue, 4 Aug 2015 10:16:57 +0200 perf/x86/intel: Handle new arch perfmon v4 status bits ArchPerfmon v4 has some new status bits in GLOBAL_STATUS. These need to be ignored when deciding whether a NMI was an NMI, to avoid eating all NMIs when they stay set, see: b292d7a10487 ("perf/x86/intel: ignore CondChgd bit to avoid false NMI handling") This patch ignores the new ASIF bit, which indicates that SGX interfered with the PMU, and also the new LBR freezing bits, which are set when the LBRs get frozen, plus the existing CondChange (set by JTAG debuggers and some buggy BIOSes) Signed-off-by: Andi Kleen Signed-off-by: Peter Zijlstra (Intel) Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: eranian@google.com Link: http://lkml.kernel.org/r/1431285767-27027-8-git-send-email-andi@firstfloor.org Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/perf_event_intel.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c index cb112bf..52c9ded 100644 --- a/arch/x86/kernel/cpu/perf_event_intel.c +++ b/arch/x86/kernel/cpu/perf_event_intel.c @@ -1611,13 +1611,14 @@ again: intel_pmu_lbr_read(); /* - * CondChgd bit 63 doesn't mean any overflow status. Ignore - * and clear the bit. + * Ignore a range of extra bits in status that do not indicate + * overflow by themselves. */ - if (__test_and_clear_bit(63, (unsigned long *)&status)) { - if (!status) - goto done; - } + status &= ~(GLOBAL_STATUS_COND_CHG | + GLOBAL_STATUS_ASIF | + GLOBAL_STATUS_LBRS_FROZEN); + if (!status) + goto done; /* * PEBS overflow sets bit 62 in the global status register -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/