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From: "Liang, Kan" <kan.liang@intel.com>
To: Andy Lutomirski <luto@amacapital.net>,
        Thomas Gleixner <tglx@linutronix.de>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "H. Peter Anvin" <hpa@zytor.com>,
        "Andrew Lutomirski" <luto@kernel.org>,
        Linus Torvalds <torvalds@linux-foundation.org>,
        Peter Zijlstra <peterz@infradead.org>,
        "Ingo Molnar" <mingo@kernel.org>
CC: "linux-tip-commits@vger.kernel.org" 
	<linux-tip-commits@vger.kernel.org>
Subject: RE: [tip:perf/core] perf/x86: Add an MSR PMU driver
Thread-Topic: [tip:perf/core] perf/x86: Add an MSR PMU driver
Thread-Index: AQHQzpQ65l/Dz0xJ8EeCrMA8u7d3Np37ZoGAgACIDlA=
Date: Tue, 4 Aug 2015 15:03:29 +0000
Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077018D16F1@SHSMSX103.ccr.corp.intel.com>
References: <1437407346-31186-1-git-send-email-kan.liang@intel.com>
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 <CALCETrXffVT=KQpURGLEAXH5x6KxXhYuicGgk3hmF8-QGT81jw@mail.gmail.com>
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> > +
> > +enum perf_msr_id {
> > +       PERF_MSR_TSC                    = 0,
> > +       PERF_MSR_APERF                  = 1,
> > +       PERF_MSR_MPERF                  = 2,
> > +       PERF_MSR_PPERF                  = 3,
> > +       PERF_MSR_SMI                    = 4,
> > +
> > +       PERF_MSR_EVENT_MAX,
> > +};
> > +
> > +struct perf_msr {
> > +       int     id;
> > +       u64     msr;
> > +};
> > +
> > +static struct perf_msr msr[] = {
> > +       { PERF_MSR_TSC, 0 },
> > +       { PERF_MSR_APERF, MSR_IA32_APERF },
> > +       { PERF_MSR_MPERF, MSR_IA32_MPERF },
> > +       { PERF_MSR_PPERF, MSR_PPERF },
> > +       { PERF_MSR_SMI, MSR_SMI_COUNT }, };
> 
> I think this could be easier to work with if it were [PERF_MSR_TSC] = {...},
> etc.  No big deal, though, until the list gets long.  However, it might make
> fixing the apparent issue below easier...
> 
> > +static int msr_event_init(struct perf_event *event) {
> > +       u64 cfg = event->attr.config;
> 
> ...
> 
> > +       event->hw.event_base = msr[cfg].msr;
> 
> Shouldn't this verify that the fancy enumeration code actually believes that
> msr[cfg] exists on this system? Otherwise we might have a very short wait
> until the perf fuzzer oopses this thing :)
> 

I think we already did the check before using msr[cfg].

> +
> +	if (cfg >= PERF_MSR_EVENT_MAX)
> +		return -EINVAL;
> +

Kan
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