Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753407AbbHDRAL (ORCPT ); Tue, 4 Aug 2015 13:00:11 -0400 Received: from smtp04.smtpout.orange.fr ([80.12.242.126]:34742 "EHLO smtp.smtpout.orange.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752375AbbHDRAJ (ORCPT ); Tue, 4 Aug 2015 13:00:09 -0400 X-ME-Helo: belgarion X-ME-Auth: amFyem1pay5yb2JlcnRAb3JhbmdlLmZy X-ME-Date: Tue, 04 Aug 2015 19:00:07 +0200 X-ME-IP: 109.214.23.104 From: Robert Jarzmik To: Ezequiel Garcia Cc: Antoine Tenart , Sebastian Hesselbarth , David Woodhouse , Brian Norris , Boris Brezillon , zmxu@marvell.com, jszhang@marvell.com, linux-arm-kernel , "linux-mtd\@lists.infradead.org" , "linux-kernel\@vger.kernel.org" Subject: Re: [PATCH v2 0/4] mtd: pxa3xx_nand: rework the timing setup References: <1436281707-20106-1-git-send-email-antoine.tenart@free-electrons.com> <20150717134159.GC10608@kwain> <55A912F0.7080605@vanguardiasur.com.ar> <87h9p2is8e.fsf@belgarion.home> <87wpxufw2v.fsf@belgarion.home> <87si81m15m.fsf@belgarion.home> X-URL: http://belgarath.falguerolles.org/ Date: Tue, 04 Aug 2015 18:56:23 +0200 In-Reply-To: (Ezequiel Garcia's message of "Mon, 3 Aug 2015 10:48:55 -0300") Message-ID: <87d1z3m1qg.fsf@belgarion.home> User-Agent: Gnus/5.130008 (Ma Gnus v0.8) Emacs/24.4 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2123 Lines: 52 Ezequiel Garcia writes: >> >> The issue I see is that : >> - there is a bug in the clk driver for pxa3xx I introduced (CKEN_AB) >> - and shutting down the GCU clock prevents the NAND from working (I can't >> explain that one yet) Ah actually it's even trickier, but it has nothing to do with the GCU clock, that was a wrong interpretation of the test sequence. What actually happens is that on the platform I have, the NAND is sharing the DFI bus with the Static Memory Controller. Now let's see what happens on boot-up, knowing that my pxa3xx-nand is a module, not builtin : - the kernel boots - the core clock initializes - the ethernet card initializes (it is on the static memory controller) - the kernel finishes the boot sequence => the NAND clock is unused => as such, the core clock framework disables it And here is the catch : on the next ethernet access, the system bus will be stalled forever. The reason behind is that because the bootloader left the "NDCR_ND_ARB_EN" bit enabled, the DFI bus sees the ethernet register access, and asks for arbitration; as the NAND clock is down, the arbitration never happens, and the pxa3xx is stalled forever. The very same thing happens when you load and unload pxa3xx-nand with a platform where it was loaded with "enable-arbiter" platform-data, and if that platform has any driver mapped in the SMC address space (0x0 .. 0x14000000). If you have an opportunity to load/unload a pxa3xx-nand, I'd be glad to have someone verify this theory. The first fix comming to my mind would be to : - disable the NDCR_ND_ARB_EN in the pxa3xx core bring up - keep enablement in pxa3xx-nand - ensure it is disabled on the probe error path or remove of pxa3xx-nand Cheers. -- Robert PS: That also means that the fix I posted for CKENA/CKENB inversion should fix the issues you see. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/