Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751971AbbHEHmM (ORCPT ); Wed, 5 Aug 2015 03:42:12 -0400 Received: from mail-yk0-f180.google.com ([209.85.160.180]:33449 "EHLO mail-yk0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751350AbbHEHmK (ORCPT ); Wed, 5 Aug 2015 03:42:10 -0400 MIME-Version: 1.0 In-Reply-To: <20150805073645.GB18700@pengutronix.de> References: <1438676218-11310-1-git-send-email-jamesjj.liao@mediatek.com> <1438676218-11310-8-git-send-email-jamesjj.liao@mediatek.com> <20150805064605.GZ18700@pengutronix.de> <20150805073645.GB18700@pengutronix.de> From: Daniel Kurtz Date: Wed, 5 Aug 2015 15:41:49 +0800 X-Google-Sender-Auth: 6iVJgnBadOkpQeINEM147I95_50 Message-ID: Subject: Re: [PATCH v6 7/9] clk: mediatek: Add subsystem clocks of MT8173 To: Sascha Hauer Cc: James Liao , Matthias Brugger , Mike Turquette , Stephen Boyd , Heiko Stubner , "open list:OPEN FIRMWARE AND..." , srv_heupstream , "linux-kernel@vger.kernel.org" , Ricky Liang , Rob Herring , linux-mediatek@lists.infradead.org, Sascha Hauer , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4107 Lines: 83 On Wed, Aug 5, 2015 at 3:36 PM, Sascha Hauer wrote: > On Wed, Aug 05, 2015 at 03:26:29PM +0800, Daniel Kurtz wrote: >> On Wed, Aug 5, 2015 at 2:46 PM, Sascha Hauer wrote: >> > On Tue, Aug 04, 2015 at 04:16:56PM +0800, James Liao wrote: >> >> Most multimedia subsystem clocks will be accessed by multiple >> >> drivers, so it's a better way to manage these clocks in CCF. >> >> This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT >> >> subsystems. >> >> >> >> Signed-off-by: James Liao >> >> --- >> >> drivers/clk/mediatek/clk-mt8173.c | 267 +++++++++++++++++++++++++++++++++ >> >> include/dt-bindings/clock/mt8173-clk.h | 97 +++++++++++- >> >> 2 files changed, 361 insertions(+), 3 deletions(-) >> >> >> >> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c >> >> index f37ace6..05335e5 100644 >> >> --- a/drivers/clk/mediatek/clk-mt8173.c >> >> +++ b/drivers/clk/mediatek/clk-mt8173.c >> >> @@ -25,6 +25,10 @@ static DEFINE_SPINLOCK(mt8173_clk_lock); >> >> static const struct mtk_fixed_clk fixed_clks[] __initconst = { >> >> FIXED_CLK(CLK_TOP_CLKPH_MCK_O, "clkph_mck_o", "clk26m", 400 * MHZ), >> >> FIXED_CLK(CLK_TOP_USB_SYSPLL_125M, "usb_syspll_125m", "clk26m", 125 * MHZ), >> >> + FIXED_CLK(CLK_TOP_DSI0_DIG, "dsi0_dig", "clk26m", 130 * MHZ), >> >> + FIXED_CLK(CLK_TOP_DSI1_DIG, "dsi1_dig", "clk26m", 130 * MHZ), >> >> + FIXED_CLK(CLK_TOP_LVDS_PXL, "lvds_pxl", "lvdspll", 148.5 * MHZ), >> >> + FIXED_CLK(CLK_TOP_LVDS_CTS, "lvds_cts", "lvdspll", 51.975 * MHZ), >> > >> > I would expect 51975 * KHZ here to avoid fractional numbers. Probably >> > gcc calculates that during compile time so this will work as expected, >> > still I'm not sure this is good style to use fractional numbers here. >> >> I thought this looked a bit strange too, but for what its worth, these >> two evaluate correctly: >> >> localhost ~ # cat /sys/kernel/debug/clk/clk_summary | grep lvds >> lvdspll 0 0 149999878 >> 0 0 >> lvds_pxl 0 0 148500000 >> 0 0 >> lvds_cts 0 0 51975000 >> 0 0 >> >> > >> > Anyway, on my system lvdspll is running at 150MHz. Are you sure there is >> > a clock derived from this running at 148.5MHz? Is it really correct to >> > use a fixed clock here or should it rather be lvdspll directly? >> >> I agree it does look strange to have a 51.975 MHz and 148.5 MHz clocks >> with a 150 MHz PLL as their parent... However, I'm not sure how much >> this matters? I think the idea here was that these frequencies are >> best effort "nominal" clock values provided by Mediatek "designers". >> The important point is that for the hardware to generate these either >> of these clocks, lvdspll must be enabled. > > This assumes that the lvdspll always runs at frequency the designers > thought that might be a good value. Should we really provide wrong clock > values when on some board for whatever reason the lvdspll is configured > for a different frequency? Do you have an alternative suggestion for estimating the frequency of a non-software controllable or measurable hardware clock? Or can we land this series and update the frequency via some future patch if and when that other board arrives which may have a different frequency - and there is some reason to care what that frequency actually is? -Dan > > sascha > > -- > Pengutronix e.K. | | > Industrial Linux Solutions | http://www.pengutronix.de/ | > Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | > Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/