Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751734AbbHELIe (ORCPT ); Wed, 5 Aug 2015 07:08:34 -0400 Received: from mail-bl2on0128.outbound.protection.outlook.com ([65.55.169.128]:22800 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751401AbbHELId (ORCPT ); Wed, 5 Aug 2015 07:08:33 -0400 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; feescale.com; dkim=none (message not signed) header.d=none; Date: Wed, 5 Aug 2015 19:08:26 +0800 From: Chenhui Zhao Subject: Re: [PATCH 3/3] PowerPC/mpc85xx: Add hotplug support on E6500 cores To: Scott Wood CC: , , , Tang Yuantian , Tang Yuantian Message-ID: <1438772906.21522.2@remotesmtp.freescale.net> In-Reply-To: <1438388531.19345.88.camel@freescale.com> References: <1438334444-31919-1-git-send-email-b29983@freescale.com> <1438334444-31919-3-git-send-email-b29983@freescale.com> <1438388531.19345.88.camel@freescale.com> X-Mailer: geary/0.10.0 MIME-Version: 1.0 Content-Type: text/plain; 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>> - unsigned long imsr1, inia1; >> + unsigned long imsr, inia; >> int nr = *(const int *)info; >> - >> - imsr1 = MSR_KERNEL; >> - inia1 = *(unsigned long *)fsl_secondary_thread_init; >> - >> - mttmr(TMRN_IMSR1, imsr1); >> - mttmr(TMRN_INIA1, inia1); >> - mtspr(SPRN_TENS, TEN_THREAD(1)); >> + int hw_cpu = get_hard_smp_processor_id(nr); >> + int thread_idx = cpu_thread_in_core(hw_cpu); >> + >> + booting_cpu_hwid = (u32)hw_cpu; > > Unnecessary cast. Please explain why you need booting_cpu_hwid. > > >> + imsr = MSR_KERNEL; >> + inia = *(unsigned long *)fsl_secondary_thread_init; >> + if (thread_idx == 0) { >> + mttmr(TMRN_IMSR0, imsr); >> + mttmr(TMRN_INIA0, inia); >> + } else { >> + mttmr(TMRN_IMSR1, imsr); >> + mttmr(TMRN_INIA1, inia); >> + } >> + mtspr(SPRN_TENS, TEN_THREAD(thread_idx)); > > Please rebase this on top of http://patchwork.ozlabs.org/patch/496952/ OK. > > >> + /* >> + * If both threads are offline, reset core to start. >> + * When core is up, Thread 0 always gets up first, >> + * so bind the current logical cpu with Thread 0. >> + */ >> + if (hw_cpu != cpu_first_thread_sibling(hw_cpu)) { >> + int hw_cpu1, hw_cpu2; >> + >> + hw_cpu1 = get_hard_smp_processor_id(primary); >> + hw_cpu2 = get_hard_smp_processor_id(primary + >> 1); >> + set_hard_smp_processor_id(primary, hw_cpu2); >> + set_hard_smp_processor_id(primary + 1, >> hw_cpu1); >> + /* get new physical cpu id */ >> + hw_cpu = get_hard_smp_processor_id(nr); > > NACK as discussed in http://patchwork.ozlabs.org/patch/454944/ > > -Scott You said, There's no need for this. I have booting from a thread1, and having it kick its thread0, working locally without messing with the hwid/cpu mapping. I still have questions here. After a core reset, how can you boot Thread1 of the core first. As I know, Thread0 boots up first by default. -Chenhui -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/