Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755575AbbHFLDO (ORCPT ); Thu, 6 Aug 2015 07:03:14 -0400 Received: from mx1.redhat.com ([209.132.183.28]:40164 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753433AbbHFLDL (ORCPT ); Thu, 6 Aug 2015 07:03:11 -0400 From: =?UTF-8?q?Marc=20Mar=C3=AD?= To: linux-kernel@vger.kernel.org Cc: Drew , Stefan Hajnoczi , "Kevin O'Connor" , Gerd Hoffmann , Laszlo , =?UTF-8?q?Marc=20Mar=C3=AD?= Subject: [PATCH] QEMU fw_cfg DMA interface documentation Date: Thu, 6 Aug 2015 13:03:07 +0200 Message-Id: <1438858987-29566-1-git-send-email-markmb@redhat.com> In-Reply-To: <1438858816-29385-1-git-send-email-markmb@redhat.com> References: <1438858816-29385-1-git-send-email-markmb@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2928 Lines: 69 Add fw_cfg DMA interface specfication in the fw_cfg documentation. Signed-off-by: Marc Marí --- Documentation/devicetree/bindings/arm/fw-cfg.txt | 36 ++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fw-cfg.txt b/Documentation/devicetree/bindings/arm/fw-cfg.txt index 953fb64..c880eec 100644 --- a/Documentation/devicetree/bindings/arm/fw-cfg.txt +++ b/Documentation/devicetree/bindings/arm/fw-cfg.txt @@ -49,6 +49,41 @@ The guest kernel is not expected to use these registers (although it is certainly allowed to); the device tree bindings are documented here because this is where device tree bindings reside in general. +Starting from revision 2, a DMA interface has also been added. This can be used +through a write-only, 64-bit wide address register. + +In this register, a pointer to a FWCfgDmaAccess structure can be written, in +big endian mode. This is the format of the FWCfgDmaAccess structure: + +typedef struct FWCfgDmaAccess { + uint64_t address; + uint32_t length; + uint32_t control; +} FWCfgDmaAccess; + +Once the address to this structure has been written, an DMA operation is +started. If the "control" field has value 2, a read operation will be performed. +"length" bytes for the current selector and offset will be mapped into the +address specified by the "address" field. + +If the field "address" has value 0, the read is considered a skip, and +the data is not copied anywhere, but the offset is still incremented. + +To check result, read the control register: + error bit set -> something went wrong. + all bits cleared -> transfer finished successfully. + otherwise -> transfer still in progress (doesn't happen + today due to implementation not being async, + but may in the future). + +Target address goes up and transfer length goes down as the transfer +happens, so after a successful transfer the length register is zero +and the address register points right after the memory block written. + +If a partial transfer happened before an error occured the address and +length registers indicate how much data has been transfered +successfully. + Required properties: - compatible: "qemu,fw-cfg-mmio". @@ -56,6 +91,7 @@ Required properties: - reg: the MMIO region used by the device. * Bytes 0x0 to 0x7 cover the data register. * Bytes 0x8 to 0x9 cover the selector register. + * From revision 2: Bytes 0xa to 0x11 cover the DMA address register. * Further registers may be appended to the region in case of future interface revisions / feature bits. -- 2.4.3 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/