Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754076AbbHFPWA (ORCPT ); Thu, 6 Aug 2015 11:22:00 -0400 Received: from bombadil.infradead.org ([198.137.202.9]:33397 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753718AbbHFPV6 (ORCPT ); Thu, 6 Aug 2015 11:21:58 -0400 Date: Thu, 6 Aug 2015 17:21:51 +0200 From: Peter Zijlstra To: "Liang, Kan" Cc: Andy Lutomirski , Thomas Gleixner , "linux-kernel@vger.kernel.org" , "H. Peter Anvin" , Andrew Lutomirski , Linus Torvalds , Ingo Molnar , "linux-tip-commits@vger.kernel.org" Subject: Re: [tip:perf/core] perf/x86: Add an MSR PMU driver Message-ID: <20150806152151.GG25159@twins.programming.kicks-ass.net> References: <1437407346-31186-1-git-send-email-kan.liang@intel.com> <37D7C6CF3E00A74B8858931C1DB2F077018D16F1@SHSMSX103.ccr.corp.intel.com> <37D7C6CF3E00A74B8858931C1DB2F077018D206A@SHSMSX103.ccr.corp.intel.com> <37D7C6CF3E00A74B8858931C1DB2F077018D2103@SHSMSX103.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <37D7C6CF3E00A74B8858931C1DB2F077018D2103@SHSMSX103.ccr.corp.intel.com> User-Agent: Mutt/1.5.21 (2012-12-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 5210 Lines: 190 On Tue, Aug 04, 2015 at 08:39:27PM +0000, Liang, Kan wrote: > Right, it could be a problem. > How about the patch as below? X-MS-Has-Attach: X-MS-TNEF-Correlator: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Your outlook wrecked it, please use a less broken MUA. How about we do the below instead? Its also virt proof by virtue of probing if we can read the MSRs. --- arch/x86/kernel/cpu/perf_event_msr.c | 122 +++++++++++------------------------ 1 file changed, 39 insertions(+), 83 deletions(-) diff --git a/arch/x86/kernel/cpu/perf_event_msr.c b/arch/x86/kernel/cpu/perf_event_msr.c index af216e9223e8..e9b6a0058110 100644 --- a/arch/x86/kernel/cpu/perf_event_msr.c +++ b/arch/x86/kernel/cpu/perf_event_msr.c @@ -10,17 +10,21 @@ enum perf_msr_id { PERF_MSR_EVENT_MAX, }; +bool test_aperfmperf(void) +{ + return boot_cpu_has(X86_FEATURE_APERFMPERF); +} + +bool test_intel(void) +{ + return boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && + boot_cpu_data.x86 == 6; +} + struct perf_msr { - int id; u64 msr; -}; - -static struct perf_msr msr[] = { - { PERF_MSR_TSC, 0 }, - { PERF_MSR_APERF, MSR_IA32_APERF }, - { PERF_MSR_MPERF, MSR_IA32_MPERF }, - { PERF_MSR_PPERF, MSR_PPERF }, - { PERF_MSR_SMI, MSR_SMI_COUNT }, + struct perf_pmu_events_attr *attr; + bool (*test)(void); }; PMU_EVENT_ATTR_STRING(tsc, evattr_tsc, "event=0x00"); @@ -29,8 +33,17 @@ PMU_EVENT_ATTR_STRING(mperf, evattr_mperf, "event=0x02"); PMU_EVENT_ATTR_STRING(pperf, evattr_pperf, "event=0x03"); PMU_EVENT_ATTR_STRING(smi, evattr_smi, "event=0x04"); +static struct perf_msr msr[] = { + [PERF_MSR_TSC] = { 0, &evattr_tsc, NULL, }, + [PERF_MSR_APERF] = { MSR_IA32_APERF, &evattr_aperf, test_aperfmperf, }, + [PERF_MSR_MPERF] = { MSR_IA32_MPERF, &evattr_mperf, test_aperfmperf, }, + [PERF_MSR_PPERF] = { MSR_PPERF, &evattr_pperf, test_intel, }, + [PERF_MSR_SMI] = { MSR_SMI_COUNT, &evattr_smi, test_intel, }, +}; + static struct attribute *events_attrs[PERF_MSR_EVENT_MAX + 1] = { &evattr_tsc.attr.attr, + NULL, }; static struct attribute_group events_attr_group = { @@ -74,6 +87,9 @@ static int msr_event_init(struct perf_event *event) event->attr.sample_period) /* no sampling */ return -EINVAL; + if (!msr[cfg].attr) + return -EINVAL; + event->hw.idx = -1; event->hw.event_base = msr[cfg].msr; event->hw.config = cfg; @@ -151,89 +167,29 @@ static struct pmu pmu_msr = { .capabilities = PERF_PMU_CAP_NO_INTERRUPT, }; -static int __init intel_msr_init(int idx) -{ - if (boot_cpu_data.x86 != 6) - return 0; - - switch (boot_cpu_data.x86_model) { - case 30: /* 45nm Nehalem */ - case 26: /* 45nm Nehalem-EP */ - case 46: /* 45nm Nehalem-EX */ - - case 37: /* 32nm Westmere */ - case 44: /* 32nm Westmere-EP */ - case 47: /* 32nm Westmere-EX */ - - case 42: /* 32nm SandyBridge */ - case 45: /* 32nm SandyBridge-E/EN/EP */ - - case 58: /* 22nm IvyBridge */ - case 62: /* 22nm IvyBridge-EP/EX */ - - case 60: /* 22nm Haswell Core */ - case 63: /* 22nm Haswell Server */ - case 69: /* 22nm Haswell ULT */ - case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */ - - case 61: /* 14nm Broadwell Core-M */ - case 86: /* 14nm Broadwell Xeon D */ - case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */ - case 79: /* 14nm Broadwell Server */ - events_attrs[idx++] = &evattr_smi.attr.attr; - break; - - case 78: /* 14nm Skylake Mobile */ - case 94: /* 14nm Skylake Desktop */ - events_attrs[idx++] = &evattr_pperf.attr.attr; - events_attrs[idx++] = &evattr_smi.attr.attr; - break; - - case 55: /* 22nm Atom "Silvermont" */ - case 76: /* 14nm Atom "Airmont" */ - case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */ - events_attrs[idx++] = &evattr_smi.attr.attr; - break; - } - - events_attrs[idx] = NULL; - - return 0; -} - -static int __init amd_msr_init(int idx) -{ - return 0; -} - static int __init msr_init(void) { - int err; - int idx = 1; + int i, j = 1; - if (boot_cpu_has(X86_FEATURE_APERFMPERF)) { - events_attrs[idx++] = &evattr_aperf.attr.attr; - events_attrs[idx++] = &evattr_mperf.attr.attr; - events_attrs[idx] = NULL; + if (!boot_cpu_has(X86_FEATURE_TSC)) { + pr_cont("no MSR PMU driver.\n"); + return 0; } - switch (boot_cpu_data.x86_vendor) { - case X86_VENDOR_INTEL: - err = intel_msr_init(idx); - break; - - case X86_VENDOR_AMD: - err = amd_msr_init(idx); - break; + /* Probe the MSRs. */ + for (i = PERF_MSR_TSC + 1; i < PERF_MSR_EVENT_MAX; i++) { + u64 val; - default: - err = -ENOTSUPP; + if (!msr[i].test() || rdmsrl_safe(msr[i].msr, &val)) + msr[i].attr = NULL; } - if (err != 0) { - pr_cont("no msr PMU driver.\n"); - return 0; + /* List remaining MSRs in the sysfs attrs. */ + for (i = 0; i < PERF_MSR_EVENT_MAX; i++) { + if (msr[i].attr) + events_attrs[j++] = &msr[i].attr->attr.attr; } + events_attrs[j] = NULL; perf_pmu_register(&pmu_msr, "msr", -1); -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/