Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933961AbbHJLEC (ORCPT ); Mon, 10 Aug 2015 07:04:02 -0400 Received: from mail-lb0-f196.google.com ([209.85.217.196]:34846 "EHLO mail-lb0-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932290AbbHJLD7 (ORCPT ); Mon, 10 Aug 2015 07:03:59 -0400 MIME-Version: 1.0 In-Reply-To: <1438933382-2936-5-git-send-email-lftan@altera.com> References: <1438933382-2936-1-git-send-email-lftan@altera.com> <1438933382-2936-5-git-send-email-lftan@altera.com> Date: Mon, 10 Aug 2015 19:03:57 +0800 Message-ID: Subject: Re: [PATCH v3 4/5] Documentation: dt-bindings: pci: altera pcie device tree binding From: Ley Foon Tan To: Bjorn Helgaas , Russell King , Marc Zyngier Cc: Arnd Bergmann , Dinh Nguyen , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Ley Foon Tan , Ley Foon Tan , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 4841 Lines: 114 On Fri, Aug 7, 2015 at 3:43 PM, Ley Foon Tan wrote: > This patch adds the bindings for Altera PCIe host controller driver and > Altera PCIe MSI driver. > > Signed-off-by: Ley Foon Tan > --- > .../devicetree/bindings/pci/altera-pcie-msi.txt | 27 ++++++++++++ > .../devicetree/bindings/pci/altera-pcie.txt | 49 ++++++++++++++++++++++ > 2 files changed, 76 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie-msi.txt > create mode 100644 Documentation/devicetree/bindings/pci/altera-pcie.txt > > diff --git a/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt > new file mode 100644 > index 0000000..7f330c9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/altera-pcie-msi.txt > @@ -0,0 +1,27 @@ > +* Altera PCIe MSI controller > + > +Required properties: > +- compatible: should contain "altr,msi-1.0" > +- reg: specifies the physical base address of the controller and > + the length of the memory mapped region. > +- reg-names: Must include the following entries: > + "csr": CSR registers > + "vector_slave": vectors region > +-interrupts: specifies the interrupt source of the parent interrupt > + controller. The format of the interrupt specifier depends on the > + parent interrupt controller. > +- num-vectors: Number of vectors, range 1 to 32. > +- msi-controller: indicates that this is MSI controller node > + > + > +Example > +msi0: msi@0xFF200000 { > + compatible = "altr,msi-1.0"; > + reg = <0xFF200000 0x00000010 > + 0xFF200010 0x00000080>; > + reg-names = "csr", "vector_slave"; > + interrupt-parent = <&hps_0_arm_gic_0>; > + interrupts = <0 42 4>; > + msi-controller = <1>; > + num-vectors = <32>; > +}; > diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt > new file mode 100644 > index 0000000..729193d > --- /dev/null > +++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt > @@ -0,0 +1,49 @@ > +* Altera PCIe controller > + > +Required properties: > +- compatible : should contain "altr,pcie-root-port-1.0" > +- reg: A list of physical base address and length for TXS and CRA. > +- reg-names: Must include the following entries: > + "Txs": TXS region > + "Cra": Control register access region > +-interrupts: specifies the interrupt source of the parent interrupt controller. > + The format of the interrupt specifier depends on the parent interrupt > + controller. > +- device_type: must be "pci" > +- #address-cells: set to <3> > +- #size-cells: set to <2> > +- #interrupt-cells: set to <1> > +- ranges: Describes the translation of addresses for root ports and standard > + PCI regions. > +- interrupt-map-mask and interrupt-map: standard PCI properties > + to define the mapping of the PCIe interface to interrupt > + numbers. > + > +Optional properties: > +- msi-parent: Link to the hardware entity that serves as the MSI controller for this PCIe > + controller. > +- bus-range: PCI bus numbers covered > + > +Example > + pcie_0: pcie@0xc00000000 { > + compatible = "altr,pcie-root-port-1.0"; > + reg = <0xc0000000 0x20000000>, > + <0xff220000 0x00004000>; > + reg-names = "Txs", "Cra"; > + interrupt-parent = <&hps_0_arm_gic_0>; > + interrupts = <0 40 4>; > + interrupt-controller; > + #interrupt-cells = <1>; > + bus-range = <0x0 0xFF>; > + device_type = "pci"; > + msi-parent = <&msi_to_gic_gen_0>; > + #address-cells = <3>; > + #size-cells = <2>; > + interrupt-map-mask = <0 0 0 7>; > + interrupt-map = <0 0 0 1 &pcie_0 1>, > + <0 0 0 2 &pcie_0 2>, > + <0 0 0 3 &pcie_0 3>, > + <0 0 0 4 &pcie_0 4>; > + ranges = <0x82000000 0x00000000 0x00000000 0xc0000000 0x00000000 0x10000000 > + 0x82000000 0x00000000 0x10000000 0xd0000000 0x00000000 0x10000000>; > + }; > -- Added DT maintainers to CC list. Please help to review if anything need to be changed. Thanks. Regards Ley Foon -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/