Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753342AbbHMQSK (ORCPT ); Thu, 13 Aug 2015 12:18:10 -0400 Received: from mail-bl2on0066.outbound.protection.outlook.com ([65.55.169.66]:64736 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752745AbbHMQSH (ORCPT ); Thu, 13 Aug 2015 12:18:07 -0400 Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Robert.Richter@caviumnetworks.com; Date: Thu, 13 Aug 2015 18:17:41 +0200 From: Robert Richter To: Marc Zyngier CC: Robert Richter , Thomas Gleixner , Jason Cooper , Tirumalesh Chalamarla , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v2 3/5] irqchip, gicv3: Workaround for Cavium ThunderX erratum 23154 Message-ID: <20150813161741.GO1820@rric.localhost> References: <1439477277-6157-1-git-send-email-rric@kernel.org> <1439477277-6157-4-git-send-email-rric@kernel.org> <55CCB393.1040909@arm.com> MIME-Version: 1.0 Content-Type: text/plain; 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On 13.08.15 16:11:15, Marc Zyngier wrote: > On 13/08/15 15:47, Robert Richter wrote: > > From: Robert Richter > > static const struct gic_capabilities gicv3_errata[] = { > > { > > + .desc = "GIC: Cavium erratum 23154", > > + .iidr = 0xa100034c, /* ThunderX pass 1.x */ > > + .iidr_mask = 0xffff0fff, > > + .init = gicv3_enable_cavium_thunderx, > > + }, > > I'm even more puzzled. You're working around a CPU bug based on the ITS > ID registers? Or have you swapped the detection methods for the two errata? :/ Right, I mixed this up... Must have starred on this for too long. Will fix that. Wrt midr: Originally this was written to support iidr. I wanted to keep the version check in the driver of the hw, an implementation outside of drivers/irqchip looked not appropriate here as it would rely then on arch arm64 only. This is the main reason. Apart from that, I think an implmentation based on struct arm64_cpu_capabilities, etc. would require much rework compared to my current easy implementation, e.g: * binding flags to callbacks and actually run them, * handing over private driver data (base addr for iidr detection) to a capabilty's match function. Overall this looked bloated. Now, that the MIDR also needs to be checked, it looked better to me to keep the gic hw detection at a single location in the driver. This also allows us to check a combination of midr and iidr values. I hope this sounds reasonable? -Robert -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/