Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932334AbbHND3J (ORCPT ); Thu, 13 Aug 2015 23:29:09 -0400 Received: from regular1.263xmail.com ([211.150.99.134]:55669 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751993AbbHND3H (ORCPT ); Thu, 13 Aug 2015 23:29:07 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: lyz@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: lyz@rock-chips.com X-UNIQUE-TAG: <5b7b1dabd2bcabed7da1ce8098bd7994> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <55CD6078.8010502@rock-chips.com> Date: Fri, 14 Aug 2015 11:28:56 +0800 From: Yunzhi Li User-Agent: Mozilla/5.0 (Windows NT 6.1; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: John Youn , "jwerner@chromium.org" , "dianders@chromium.org" CC: "huangtao@rock-chips.com" , "cf@rock-chips.com" , "hl@rock-chips.com" , "wulf@rock-chips.com" , "gregory.herrero@intel.com" , "linux-rockchip@lists.infradead.org" , Greg Kroah-Hartman , "linux-usb@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v1 1/3] usb: dwc2: reset AHB hclk domain before init References: <1439279787-26674-1-git-send-email-lyz@rock-chips.com> <2B3535C5ECE8B5419E3ECBE300772909017528DC44@US01WEMBX2.internal.synopsys.com> In-Reply-To: <2B3535C5ECE8B5419E3ECBE300772909017528DC44@US01WEMBX2.internal.synopsys.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2407 Lines: 62 在 2015/8/14 8:09, John Youn 写道: > On 8/11/2015 12:57 AM, Yunzhi Li wrote: >> We initiate dwc2 usb controller in BIOS, when kernel driver >> start-up we should reset AHB hclk domain to reset all AHB >> interface registers to default. Without this the FIFO value >> setting might be incorrect because calculating FIFO size need the >> power-on value of GRXFSIZ/GNPTXFSIZ/HPTXFSIZ registers. >> >> This patch could avoid warnning massage like in rk3288 platform: >> [ 2.074764] dwc2 ff580000.usb: 256 invalid for >> host_perio_tx_fifo_size. Check HW configuration. >> >> ...... > I didn't receive the other two patches in this series so I was > confused about where the "ahb_reset" was coming from when I > replied to your other patch. > > I see you changed the name and documented the DT so never mind. > > Another thing is that there probably shouldn't be a debug > message on the IS_ERR condition since that is the common case > and of no interest to other platforms. > > The other two resets you added aren't used by the driver > anywhere right? Maybe those should be left out until they are. > > John > Hi John , Here is the other two patches : https://patchwork.kernel.org/patch/6989541/ https://patchwork.kernel.org/patch/6989531/ ahb_reset is hreset_n signal of dwc2 IP. Our rk3288 SoC implement connect this signal to a special register in clock ang reset unit (CRU) module, set this register will reset dwc2 control and status registers(CSR) to default value. You could find more info in <> 4.4.1 System Clock and Reset Signals. Our problem is that dwc2_get_hwparams() reads fifo size registers and reguards it as the power-on reset value, then dwc2_set_param_host_perio_tx_fifo_size() will check this value and make sure the new fifo size value is no bigger than the power-on reset value. But we init and set these fifo registers in BIOS, so here hw->xxx_fifo_size is not the real power-on reset vaule. So we hope to reset CSR before dwc2_get_hwparams(). I have another ideal: we might use GRSTCTL.CSftRst instead of hreset_n to reset dwc2 CSR. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/