Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754828AbbHQL47 (ORCPT ); Mon, 17 Aug 2015 07:56:59 -0400 Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:33765 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750937AbbHQL45 (ORCPT ); Mon, 17 Aug 2015 07:56:57 -0400 Date: Mon, 17 Aug 2015 13:56:55 +0200 From: Pavel Machek To: atull@opensource.altera.com Cc: gregkh@linuxfoundation.org, jgunthorpe@obsidianresearch.com, hpa@zytor.com, monstr@monstr.eu, michal.simek@xilinx.com, rdunlap@infradead.org, Moritz Fischer , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, pantelis.antoniou@konsulko.com, robh+dt@kernel.org, grant.likely@linaro.org, iws@ovro.caltech.edu, linux-doc@vger.kernel.org, broonie@kernel.org, philip@balister.org, rubini@gnudd.com, s.trumtrar@pengutronix.de, jason@lakedaemon.net, kyle.teske@ni.com, nico@linaro.org, balbi@ti.com, m.chehab@samsung.com, davidb@codeaurora.org, rob@landley.net, davem@davemloft.net, cesarb@cesarb.net, sameo@linux.intel.com, akpm@linux-foundation.org, linus.walleij@linaro.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, devel@driverdev.osuosl.org, Petr Cvek , delicious.quinoa@gmail.com, dinguyen@opensource.altera.com Subject: Re: [PATCH v10 8/8] staging: add simple-fpga-bus Message-ID: <20150817115655.GB434@amd> References: <1439487452-23977-1-git-send-email-atull@opensource.altera.com> <1439487452-23977-10-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1439487452-23977-10-git-send-email-atull@opensource.altera.com> User-Agent: Mutt/1.5.23 (2014-03-12) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1042 Lines: 25 On Thu 2015-08-13 12:37:32, atull@opensource.altera.com wrote: > From: Alan Tull > > Add simple fpga bus. This is a bus that configures an fpga and its > bridges before populating the devices below it. This is intended > for use with device tree overlays. > > Note that FPGA bridges are seen as reset controllers so no special > framework for FPGA bridges will need to be added. > > This supports fpga use where hardware blocks on a fpga will need > drivers (as opposed to fpga used as an acceleration without drivers.) > > Signed-off-by: Alan Tull 7,8: Acked-by: Pavel Machek -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/