Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752259AbbHTIDt (ORCPT ); Thu, 20 Aug 2015 04:03:49 -0400 Received: from mail-out.m-online.net ([212.18.0.10]:57845 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751245AbbHTIDn (ORCPT ); Thu, 20 Aug 2015 04:03:43 -0400 X-Auth-Info: uoyuWYhe6b2P7p9e/wbj2v69DqqdIER5AN7D8pFjyNQ= From: Marek Vasut To: Viet Nga Dao Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver Date: Thu, 20 Aug 2015 09:55:19 +0200 User-Agent: KMail/1.13.7 (Linux/3.14-2-amd64; KDE/4.13.1; x86_64; ; ) Cc: Brian Norris , David Woodhouse , "devicetree@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "nga_chi86" References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Message-Id: <201508200955.20067.marex@denx.de> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2332 Lines: 63 On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: > Hi, Hi, > >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: > >>> I'm not very helpful here, so hopefully Viet can be of more use: > >> Yup :) > >> > >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: > >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: > >>> > Also, I cannot find any documentation for this IP block even if I > >>> > search through Quartus/QSys, is there any proper documentation > >>> > available anywhere? > >>> > >>> I never found proper documentation, but I didn't look too hard. I've > >>> mostly been going off of Viet's comments and code. > >> > >> Me neither, and I looked through the altera stuff in fact. I'm trying to > >> learn whether this is just an Soft IP, in which case it certainly can > >> be fixed ; or if there is actually some chip shipping with this crap > >> synthesised into actual silicon. > >> > >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ > >>> flash here: > >>> > >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera > >>> ture/ > >>> hb/cfg/cfg_cf52012.pdf > >> > >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just > >> have different JEDEC >ID and are a bit more expensive. > > > > You can find the document at here > > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu > > re/ug/ug_embedded_ip.pdf) > > > > Chapter 42.Page 407. > > > > For the soft IP issue, i've requested hardware engineer to come out > > the solution. That's good :) > > So in the mean way, our driver will NOT support Micron > > flashes until hardware fix is completed. This doesn't answer my question, so let me reiterate. Is this controller only Soft IP (as in, FPGA core) or is this controller shipping in some chip as Hard IP (as in, piece of silicon) ? > > Hence, i just submitted version 5 for this driver with eliminating > > micron device support. Hope this version will get ACKed by you. We'll see. Best regards, Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/