Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752721AbbHTIGm (ORCPT ); Thu, 20 Aug 2015 04:06:42 -0400 Received: from mail-ob0-f176.google.com ([209.85.214.176]:34395 "EHLO mail-ob0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752696AbbHTIGb (ORCPT ); Thu, 20 Aug 2015 04:06:31 -0400 MIME-Version: 1.0 In-Reply-To: <201508200955.20067.marex@denx.de> References: <201508200955.20067.marex@denx.de> Date: Thu, 20 Aug 2015 16:06:29 +0800 Message-ID: Subject: Re: [PATCH] [PATCH v4] mtd:spi-nor: Add Altera Quad SPI Driver From: Viet Nga Dao To: Marek Vasut Cc: Viet Nga Dao , Brian Norris , David Woodhouse , "devicetree@vger.kernel.org" , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2481 Lines: 67 On Thu, Aug 20, 2015 at 3:55 PM, Marek Vasut wrote: > On Thursday, August 20, 2015 at 09:37:33 AM, Viet Nga Dao wrote: >> Hi, > > Hi, > >> >> On Tuesday, August 18, 2015 at 03:24:44 AM, Brian Norris wrote: >> >>> I'm not very helpful here, so hopefully Viet can be of more use: >> >> Yup :) >> >> >> >>> On Mon, Aug 17, 2015 at 07:53:23PM +0200, Marek Vasut wrote: >> >>> > On Monday, August 17, 2015 at 06:03:38 PM, Brian Norris wrote: >> >>> > Also, I cannot find any documentation for this IP block even if I >> >>> > search through Quartus/QSys, is there any proper documentation >> >>> > available anywhere? >> >>> >> >>> I never found proper documentation, but I didn't look too hard. I've >> >>> mostly been going off of Viet's comments and code. >> >> >> >> Me neither, and I looked through the altera stuff in fact. I'm trying to >> >> learn whether this is just an Soft IP, in which case it certainly can >> >> be fixed ; or if there is actually some chip shipping with this crap >> >> synthesised into actual silicon. >> >> >> >>> But FWIW, I did find some relevant info for the peculiar Altera EPCQ >> >>> flash here: >> >>> >> >>> https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/litera >> >>> ture/ >> >>> hb/cfg/cfg_cf52012.pdf >> >> >> >> Altera EPCS/EPCQ flashes are just rebranded micron flashes, they just >> >> have different JEDEC >ID and are a bit more expensive. >> > >> > You can find the document at here >> > (https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literatu >> > re/ug/ug_embedded_ip.pdf) >> > >> > Chapter 42.Page 407. >> > >> > For the soft IP issue, i've requested hardware engineer to come out >> > the solution. > > That's good :) > >> > So in the mean way, our driver will NOT support Micron >> > flashes until hardware fix is completed. > > This doesn't answer my question, so let me reiterate. Is this controller > only Soft IP (as in, FPGA core) or is this controller shipping in some > chip as Hard IP (as in, piece of silicon) ? > This is new soft IP. >> > Hence, i just submitted version 5 for this driver with eliminating >> > micron device support. Hope this version will get ACKed by you. > > We'll see. > > Best regards, > Marek Vasut -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/