Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755676AbbHYL4f (ORCPT ); Tue, 25 Aug 2015 07:56:35 -0400 Received: from foss.arm.com ([217.140.101.70]:40791 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755382AbbHYLxj (ORCPT ); Tue, 25 Aug 2015 07:53:39 -0400 From: Marc Zyngier To: Thomas Gleixner , Jason Cooper Cc: Christoffer Dall , Jiang Liu , Eric Auger , , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/4] irqchip: GICv2/v3: Add support for irq_vcpu_affinity Date: Tue, 25 Aug 2015 12:53:21 +0100 Message-Id: <1440503605-10185-1-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 2.1.4 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 3078 Lines: 76 The GICv2 and GICv3 architectures allow an active physical interrupt to be forwarded to a guest, and the guest to indirectly perform the deactivation of the interrupt by performing an EOI on the virtual interrupt (see for example the GICv2 spec, 3.2.1). This allows some substantial performance improvement for level triggered interrupts that otherwise have to be masked/unmasked in VFIO, not to mention the required trap back to KVM when the guest performs an EOI. To enable this, the GICs need to be switched to a different EOImode, where a taken interrupt can be left "active" (which prevents the same interrupt from being taken again), while other interrupts are still being processed normally. We also use the new irq_set_vcpu_affinity hook that was introduced for Intel's "Posted Interrupts" to determine whether or not to perform the deactivation at EOI-time. As all of this only makes sense when the kernel can behave as a hypervisor, we only enable this mode on detecting that the kernel was actually booted in HYP mode, and that the GIC supports this feature. This series is a complete rework of a RFC I sent over a year ago: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-June/266328.html Since then, a lot has been either merged (the irqchip_state) or reworked (my active-timer series: http://www.spinics.net/lists/kvm/msg118768.html), and this implements the last few bits for Eric Auger's series to finally make it into the kernel: https://lkml.org/lkml/2015/7/2/268 https://lkml.org/lkml/2015/7/6/291 With all these patches combined, physical interrupt routing from the kernel into a VM becomes possible. This has been tested on Juno (GICv2) and FastModel (GICv3), and Eric tested it on a Calxeda Midway. A branch is available at: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git irq/gic-irq-vcpu-affinity-v2 * From v2: - Another small fix from Eric - Some commit message cleanups * From v1: - Fixes after review from Eric - Got rid of the cascaded GICv2 hack (it was broken anyway) - Folded the LPI deactivation patch (it makes more sense as part of the main one. - Some clarifying comments about the "deactivate on mask" - I haven't retained Eric's Reviewed/Tested-by, as the code as significantly changed on GICv2 Marc Zyngier (4): irqchip: GICv3: Convert to EOImode == 1 irqchip: GICv3: Don't deactivate interrupts forwarded to a guest irqchip: GIC: Convert to EOImode == 1 irqchip: GIC: Don't deactivate interrupts forwarded to a guest drivers/irqchip/irq-gic-v3.c | 70 +++++++++++++++++++++-- drivers/irqchip/irq-gic.c | 111 ++++++++++++++++++++++++++++++++++++- include/linux/irqchip/arm-gic-v3.h | 9 +++ include/linux/irqchip/arm-gic.h | 4 ++ 4 files changed, 188 insertions(+), 6 deletions(-) -- 2.1.4 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/