Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932856AbbHZJMi (ORCPT ); Wed, 26 Aug 2015 05:12:38 -0400 Received: from devils.ext.ti.com ([198.47.26.153]:49816 "EHLO devils.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbbHZJMY (ORCPT ); Wed, 26 Aug 2015 05:12:24 -0400 Message-ID: <55DD82EA.6090300@ti.com> Date: Wed, 26 Aug 2015 14:42:10 +0530 From: Sekhar Nori User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.8.0 MIME-Version: 1.0 To: Sebastian Andrzej Siewior , CC: , , , Subject: Re: [RFC 3/3] serial: 8250_omap: try to avoid IER_RDI with DMA References: <1439568064-7907-1-git-send-email-bigeasy@linutronix.de> <1439568064-7907-3-git-send-email-bigeasy@linutronix.de> In-Reply-To: <1439568064-7907-3-git-send-email-bigeasy@linutronix.de> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1990 Lines: 39 On Friday 14 August 2015 09:31 PM, Sebastian Andrzej Siewior wrote: > It has been observed on DRA7-evm that the UART triggers the interrupt and > reading IIR says IIR_NO_INT. It seems that we receive data via RX-DMA > but the interrupt is triggered anyway. I have hardly observed it on > AM335x and not in *that* quantity. On DRA7-evm with continuous transfers > at 3MBaud and CPU running at 1.5Ghz it is possible that the IRQ-core will > close the UART interrupt after "some time" with "nobody cared". > > I've seen that by not enabling IER_RDI those spurious interrupts are not > triggered. Also it seems that DMA and RDI cause the "timeout interrupt" > which does not allow RX-DMA to be scheduled even if the FIFO reached the > programmed RX threshold. However without RDI we don't get a notification > if we have less than RX threshold bytes in the FIFO. > This is where we have the rx_dma_wd timer. After programming the RX-DMA > transfer wait HZ / 4 or 250ms for it to complete. If it does not > complete in that time span we cancel the DMA transfer and enable RDI. > RDI will trigger an UART interrupt in case we have bytes in the FIFO. > Once we read bytes manually from the FIFO we enable RX-DMA again > (without RDI) with the same 250ms timeout. > > One downside with this approach is that latency sensitive protocols that > transfer less than 48 bytes will have to wait 250ms to complete. I guess because of this reason, wlink8 bluetooth connected to TI's DRA7 EVM failed to probe with this patch included. At the least, looks like this patch needs some tuning. > > Is there maybe a user interface where one could set small or bulk transfers? > > Signed-off-by: Sebastian Andrzej Siewior Thanks, Sekhar -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/