Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753195AbbHZQcY (ORCPT ); Wed, 26 Aug 2015 12:32:24 -0400 Received: from mail-by2on0127.outbound.protection.outlook.com ([207.46.100.127]:14687 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751690AbbHZQcQ (ORCPT ); Wed, 26 Aug 2015 12:32:16 -0400 From: Shenwei Wang To: Thomas Gleixner CC: "shawn.guo@linaro.org" , "jason@lakedaemon.net" , "sudeep.holla@arm.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Huang Anson Subject: RE: [PATCH 1/1] irqchip: imx-gpcv2: Simplify the implemenation Thread-Topic: [PATCH 1/1] irqchip: imx-gpcv2: Simplify the implemenation Thread-Index: AQHQ4BhnQCw9/HJgNUCrRbRu4Kf4sJ4ecbkw Date: Wed, 26 Aug 2015 16:32:11 +0000 Message-ID: References: <1440604166-2624-1-git-send-email-shenwei.wang@freescale.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Shenwei.Wang@freescale.com; x-originating-ip: [192.88.168.50] x-microsoft-exchange-diagnostics: 1;BLUPR03MB1362;5:GvDUFH1eSleQbsovB5I4pDAzZ3JyuDPv8CflNcYxoTkg+dPUyF2nthIHOUIrkXozaDTTu2D9aS+fHHOte0p5KRf4wLaOEV4z+lMy5BL4mZxUo+xoFzOOp27jzMzt781Ss7GQMyD15sny9//KRX9tUg==;24:mCXJBNJgaLWsJfRFIriphxRzE5+bWtOkgNpx0eKTBPeCq9YOGWZDjANh2Na725syyB5PgyDske4A0/lHUOA6fFRHrZghshRTtY+FcgzfYAY=;20:1cfQMzdvN1WLxsK3wDUZIB/hUrU67exzzubUspOF2JgcYpqjc4Hvaa2d2+DYqVupUO7rwmOlyrW6N9pcq8R8AA== x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1362; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(8121501046)(5005006)(3002001);SRVR:BLUPR03MB1362;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1362; x-forefront-prvs: 0680FADD48 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(13464003)(164054003)(199003)(189002)(24454002)(54356999)(77156002)(62966003)(46102003)(99286002)(50986999)(2900100001)(2950100001)(76176999)(106356001)(68736005)(101416001)(122556002)(64706001)(5007970100001)(76576001)(5004730100002)(5003600100002)(40100003)(66066001)(5002640100001)(19580395003)(19580405001)(189998001)(81156007)(4001540100001)(77096005)(97736004)(2656002)(102836002)(10400500002)(5001860100001)(5001830100001)(5001920100001)(86362001)(87936001)(5001960100002)(110136002)(33656002)(107886002)(106116001)(92566002)(74316001)(105586002)(4001430100001);DIR:OUT;SFP:1102;SCL:1;SRVR:BLUPR03MB1362;H:CY1PR0301MB0843.namprd03.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; Content-Type: text/plain; charset="gb2312" MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2015 16:32:12.0507 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BLUPR03MB1362 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id t7QGWaGd026405 Content-Length: 1633 Lines: 54 > -----Original Message----- > From: Thomas Gleixner [mailto:tglx@linutronix.de] > Sent: 2015??8??26?? 11:00 > To: Wang Shenwei-B38339 > Cc: shawn.guo@linaro.org; jason@lakedaemon.net; sudeep.holla@arm.com; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; Huang > Yongcai-B20788 > Subject: Re: [PATCH 1/1] irqchip: imx-gpcv2: Simplify the implemenation > > On Wed, 26 Aug 2015, Shenwei Wang wrote: > > u32 imx_gpcv2_get_wakeup_source(u32 **sources) { > > - if (!imx_gpcv2_instance) > > + struct gpcv2_irqchip_data *cd; > > + void __iomem *reg; > > + int i; > > + > > + cd = imx_gpcv2_instance; > > + if (!cd) > > return 0; > > > > + for (i = 0; i < IMR_NUM; i++) { > > + reg = cd->gpc_base + cd->cpu2wakeup + i * 4; > > + cd->wakeup_sources[i] = readl_relaxed(reg); > > + } > > + > > if (sources) > > - *sources = imx_gpcv2_instance->wakeup_sources; > > + *sources = cd->wakeup_sources; > > > > return IMR_NUM; > > You do not need the intermediate storage at all. > > u32 imx_gpcv2_get_wakeup_source(u32 *sources) { > if (sources) { > for (i = 0; i < IMR_NUM; i++) { > reg = cd->gpc_base + cd->cpu2wakeup + i * 4; > sources[i] = readl_relaxed(reg); > } > } > .... Using the intermediate storage here can make the caller a little easier, because the caller does not need to malloc the memory before the call. Especially the caller does not even know how many memory to allocate In the beginning. Thanks, Shenwei > Hmm? ????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?