Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752293AbbH0Dgl (ORCPT ); Wed, 26 Aug 2015 23:36:41 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:40177 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750773AbbH0Dgk (ORCPT ); Wed, 26 Aug 2015 23:36:40 -0400 From: Andy Gross To: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Andy Gross Subject: [PATCH] arm64: dts: qcom: Add 8x16 Serial UART1 node Date: Wed, 26 Aug 2015 22:36:20 -0500 Message-Id: <1440646580-28241-1-git-send-email-agross@codeaurora.org> X-Mailer: git-send-email 1.7.9.5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2829 Lines: 104 This patch adds the nodes required to support the UART1 node on the MSM8916. Signed-off-by: Andy Gross --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 8 +++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 35 ++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index 98abece..3cc53a7 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -19,6 +19,7 @@ / { aliases { serial0 = &blsp1_uart2; + serial1 = &blsp1_uart1; }; chosen { @@ -26,6 +27,13 @@ }; soc { + serial@78af000 { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart1_default>; + pinctrl-1 = <&blsp1_uart1_sleep>; + }; + serial@78b0000 { status = "okay"; pinctrl-names = "default", "sleep"; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 0f49ebd..ba64447 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -91,6 +91,30 @@ interrupt-controller; #interrupt-cells = <2>; + blsp1_uart1_default: blsp1_uart1_default { + pinmux { + function = "blsp_uart1"; + pins = "gpio0", "gpio1"; + }; + pinconf { + pins = "gpio0", "gpio1"; + drive-strength = <16>; + bias-disable; + }; + }; + + blsp1_uart1_sleep: blsp1_uart1_sleep { + pinmux { + function = "gpio"; + pins = "gpio0", "gpio1"; + }; + pinconf { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + blsp1_uart2_default: blsp1_uart2_default { pinmux { function = "blsp_uart2"; @@ -105,7 +129,7 @@ blsp1_uart2_sleep: blsp1_uart2_sleep { pinmux { - function = "blsp_uart2"; + function = "gpio"; pins = "gpio4", "gpio5"; }; pinconf { @@ -123,6 +147,15 @@ reg = <0x1800000 0x80000>; }; + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x78af000 0x200>; + interrupts = ; + clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + blsp1_uart2: serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x78b0000 0x200>; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/