Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752105AbbKBH5t (ORCPT ); Mon, 2 Nov 2015 02:57:49 -0500 Received: from mail-am1on0069.outbound.protection.outlook.com ([157.56.112.69]:32896 "EHLO emea01-am1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751576AbbKBH5s (ORCPT ); Mon, 2 Nov 2015 02:57:48 -0500 From: Noam Camus To: Daniel Lezcano , "linux-snps-arc@lists.infradead.org" CC: "linux-kernel@vger.kernel.org" , Tal Zilcer , Gil Fruchter , Chris Metcalf , Rob Herring , John Stultz , Thomas Gleixner Subject: RE: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Thread-Topic: [PATCH v1 02/20] clocksource: Add NPS400 timers driver Thread-Index: AQHRE951aFhaJcfF3ku8/lfO2RvsuZ6HpGKAgACoonA= Date: Mon, 2 Nov 2015 07:57:43 +0000 Message-ID: References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> <1446297327-16298-3-git-send-email-noamc@ezchip.com> <5636799B.50307@linaro.org> In-Reply-To: <5636799B.50307@linaro.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=noamc@ezchip.com; x-originating-ip: [212.179.42.66] x-microsoft-exchange-diagnostics: 1;DB5PR02MB0774;5:FE3DZqZKCZ0D2ad87nrBnsNYQD63Oqa6bdsHPVfHEHL2M/j9ZzBN55pPCNoAiEzJJ5oBQHHTkTuk5fga3bfMNq/EvLRq2cNR5XEFPVvKocnR9qo0/puwIim9g37KvUdK8MOUBpQMp38U2h8UtSV36g==;24:WEA9fncC0DaSSQrQwTB+/z2mobN8lmt+9M7PftN+xkGBgvG+WxXxhsKOAvMNx1jIEMaB9cc5usztQSEageQp+EDcBlGVUukxlFONzO2Rhwk=;20:iQ9XY0orxC9XmO19v2IR/kEm1gka0ZozLic/yp6F8/DVcDBtyGdrWzJxbdrs5A5pA5Pl9j1f57lkkOQ+0eigXg== x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DB5PR02MB0774; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(5005006)(8121501046)(520078)(3002001)(10201501046);SRVR:DB5PR02MB0774;BCL:0;PCL:0;RULEID:;SRVR:DB5PR02MB0774; x-forefront-prvs: 0748FF9A04 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(377454003)(189002)(199003)(164054003)(2501003)(86362001)(10400500002)(5004730100002)(5007970100001)(97736004)(5001770100001)(40100003)(19580405001)(81156007)(19580395003)(122556002)(106356001)(106116001)(105586002)(66066001)(77096005)(74316001)(5003600100002)(2950100001)(102836002)(5002640100001)(76576001)(87936001)(2900100001)(15975445007)(101416001)(5001960100002)(50986999)(76176999)(54356999)(92566002)(5008740100001)(189998001)(33656002);DIR:OUT;SFP:1101;SCL:1;SRVR:DB5PR02MB0774;H:DB5PR02MB1141.eurprd02.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-MS-Exchange-CrossTenant-originalarrivaltime: 02 Nov 2015 07:57:43.6324 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 0fc16e0a-3cd3-4092-8b2f-0a42cff122c3 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB5PR02MB0774 X-Microsoft-Exchange-Diagnostics: 1;DB5PR02MB1240;2:2aiNpuKXpQMTEqTgu2TMVwC7lTpdmgMxDnc1k8ofCDg6JDCsNuUEF9O/tOEWcDuL+TmPbfa4eOriwX6/ie4q0F3w/8smvHxJUyi/knOPLYiIWot00f9AhzulwGUUcqT+svaGM4F7/YuvfYJ3iWF3xPdB962uNwSU1VeXLnP1+PA=;23:6K6CpVI1YWeMpuamqfZVuArCBqzGDUDOhIzx6mG8TNLu3wtGMX3piZ2+xg7NMERFRDYOCIBMLaChj1nkjJtykNpLN7x66bLHm1GzEsxLIpc1NzfBPZC/onUF7Zfj9YFcF0dOAklVERtgpCBiZDa2zkD7tMb7JKrYR/lTLdynAFIZfuhR+GnX00apzHPKLDnU X-OriginatorOrg: ezchip.com Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id tA27vsIE029989 Content-Length: 847 Lines: 25 > From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org] > Sent: Sunday, November 01, 2015 10:44 PM > Please add an entry in the clocksource's Kconfig. > eg: OK > Are you sure all the headers are needed ? Thanks, will revise this part. > Why do you need to disable the interrupt here ? Thanks, seem like left over from past issue, I will remove. > May be you can consider using only the 32bits. Sometimes it is faster than using 64bits arithmetic and reading the register three times. > https://lkml.org/lkml/2014/6/20/431 Our device can reach 1000MHz. That means that the 32-bit half of the counter rolls over every ~4 seconds. I am not sure optimization is justified. -Noam ????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?