Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753807AbbKCEie (ORCPT ); Mon, 2 Nov 2015 23:38:34 -0500 Received: from mail-pa0-f44.google.com ([209.85.220.44]:35011 "EHLO mail-pa0-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751801AbbKCEib (ORCPT ); Mon, 2 Nov 2015 23:38:31 -0500 Date: Mon, 2 Nov 2015 20:38:27 -0800 From: Brian Norris To: Yakir Yang Cc: Inki Dae , Andrzej Hajda , Joonyoung Shim , Seung-Woo Kim , Kyungmin Park , Jingoo Han , Thierry Reding , Krzysztof Kozlowski , Rob Herring , Heiko Stuebner , Mark Yao , djkurtz@chromium.org, dianders@chromium.org, Gustavo Padovan , linux-samsung-soc@vger.kernel.org, Russell King , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , javier@osg.samsung.com, Kukjin Kim , robherring2@gmail.com, devicetree@vger.kernel.org, Pawel Moll , Ian Campbell , Sean Paul , dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Kumar Gala , ajaynumb@gmail.com, Andy Yan Subject: Re: [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Message-ID: <20151103043827.GA17261@localhost> References: <1446020143-32645-1-git-send-email-ykk@rock-chips.com> <1446083918-30809-1-git-send-email-ykk@rock-chips.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1446083918-30809-1-git-send-email-ykk@rock-chips.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2536 Lines: 84 Hi Yakir, On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote: > Add phy driver for the Rockchip DisplayPort PHY module. This > is required to get DisplayPort working in Rockchip SoCs. > > Reviewed-by: Heiko Stuebner > Signed-off-by: Yakir Yang > --- ... > diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c > new file mode 100644 > index 0000000..f3e0058 > --- /dev/null > +++ b/drivers/phy/phy-rockchip-dp.c > @@ -0,0 +1,151 @@ > +/* > + * Rockchip DP PHY driver > + * > + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd. > + * Author: Yakir Yang > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define GRF_SOC_CON12 0x0274 > + > +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4) > +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4) Why are the above two macros the same? Judging by the RK3288 manual and other downstream drivers, it seems like you want the _MASK one to be shifted left by 16 (i.e., BIT(20)). > + > +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21) > +#define GRF_EDP_PHY_SIDDQ_ON 0 > +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5) > + ... > + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER | > + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK); IOW, the above is writing: BIT(4) | BIT(4) whereas I think you want: BIT(4) | BIT(20) > + if (ret != 0) { > + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret); > + return ret; > + } > + ... (FYI, I came across this by inspection when comparing Heiko's 'somewhat-stable' branch [1] with this series. The former brings up eDP fine on veyron-jaq, whereas this one doesn't yet, even with the above change. Still debugging the issue.) Brian [1] https://github.com/mmind/linux-rockchip/tree/devel/somewhat-stable -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/