Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755261AbbKCRSb (ORCPT ); Tue, 3 Nov 2015 12:18:31 -0500 Received: from mail-by2on0099.outbound.protection.outlook.com ([207.46.100.99]:2992 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753549AbbKCRSM (ORCPT ); Tue, 3 Nov 2015 12:18:12 -0500 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; lwn.net; dkim=none (message not signed) header.d=none;lwn.net; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=atull@opensource.altera.com; From: To: Rob Herring CC: Moritz Fischer , Josh Cartwright , , , , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Jonathan Corbet , , , , , , , Alan Tull Subject: [PATCH v13 1/6] fpga: add usage documentation for simple fpga bus Date: Tue, 3 Nov 2015 11:10:59 -0600 Message-ID: <1446570664-10293-2-git-send-email-atull@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1446570664-10293-1-git-send-email-atull@opensource.altera.com> References: <1446570664-10293-1-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY1PR0201CA0009.namprd02.prod.outlook.com (25.160.191.147) To BLUPR03MB1507.namprd03.prod.outlook.com (25.163.81.25) X-Microsoft-Exchange-Diagnostics-untrusted: 1;BLUPR03MB1507;2:YAy9s3Ls9rClck48ePw7OPLFzIpdAp1by+MRh3SZnlKZrXFd2UTL65xuZAdgan6KLRwBTyH68Ub9DLFeRzYP0uTCX7xZZ7WqQEAz9h9S+yA1zpJCMLvEvUWSeNZXL3KZSMSgpinxOGQOVP6Oz9KPNkj57p3PDQLt1hgCWTW8/bw=;3:7karxLc9uv31dj289CaCkNzuNxPp8g9YOiGJippcfGdCNYsEaLkzdcIKsMmgol0v4CVtigf8R7X63d0UQgpojMHyb6I8XLTdt5V/onp0Fasq/5XvIAtU3FPyoKSXd1aMyCH/7YqYOlGBOWiJpodISw==;25:wIrhIpj21sSL+2X6kTEBYFk06ctKyJ/IjL5kJe0WeNZYNv5UIw4vgdFt7oUWDQbnrhnbON+7gdMNNBPky1+Gxqogy78cP2cuP4ZsaKWgNtFddofnpfsSnyTxAKtRj+PAFZycuynbGlQ9aTjgm0lkjMtF35MHytk4UvV1KqMzQM9FjaxzoVviv7M+kpj68EKGyBIyxsgZMV6HhvY1Z4hlJ9UKdrH21PvjhatfKqIPxB8LNjD386PY6BKWf8PTzGl1SyLFN3Lv88uQOqfBJl3fmA==;20:5GXGSXYbpIR/iWtlySfXiJx3C8gSAqsVFurWEjm/qAzkJ5mvfVZTFwsYt/fbVgNVJv43RCr71nm58jx9uzdo+pavZR6pqTggzKJ6Y4KcHvkFOhdhPHJdxD4whKcnhVo2ZqtU75/J/joS11LF0Ij6qmSBpTQxcXUWQxZLd+AkyjI= X-Microsoft-Antispam-Untrusted: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1507; 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Signed-off-by: Alan Tull Reviewed-by: Moritz Fischer --- v9: Initial version of this patch in patchset v10: s/fpga/FPGA/g improve formatting some rewriting move to staging/simple-fpga-bus v11: No change in this patch for v11 of the patch set v12: Moved out of staging Small changes due to using FPGA bridge framework and not representing the bridges as resets. v13: Fix some nits --- Documentation/fpga/simple-fpga-bus.txt | 58 ++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/fpga/simple-fpga-bus.txt diff --git a/Documentation/fpga/simple-fpga-bus.txt b/Documentation/fpga/simple-fpga-bus.txt new file mode 100644 index 0000000..9b04826 --- /dev/null +++ b/Documentation/fpga/simple-fpga-bus.txt @@ -0,0 +1,58 @@ +Simple FPGA Bus + +Alan Tull 2015 + +Overview +======== + +The simple FPGA bus adds device tree overlay support for FPGAs. Loading a DT +overlay will result in the FPGA getting programmed with an image, its bridges +will be released, and the DT populated for nodes below the simple-fpga-bus. +This results in drivers getting probed for the hardware that just got added. +This is intended to support the FPGA usage where the FPGA has hardware that +requires drivers. Removing the overlay will result in the drivers getting +removed and the bridges being disabled. + +The simple FPGA bus will need to disable and enable bridges that will only +affect the child devices that are below the bus. If partial reconfiguration +is to be done, then bridges will need to be added within the FPGA design to +protect the rest of the bus when one part of the FPGA design is being +reconfigured. + + +Sequence +======== + +Load the DT overlay. One way to do that from user space is to use Pantelis' +DT-Overlay configfs interface. + +This causes the simple FPGA bus to be probed and will do the following: + 1. Disable the FPGA bridges. + 2. Call the FPGA manager core to program the FPGA. + 3. Release the FPGA bridges. + 4. Call of_platform_populate resulting in device drivers getting probed. + + +Requirements +============ + + 1. An FPGA image that has a hardware block or blocks that use drivers that are + supported in the kernel. + 2. A device tree overlay (example is in the simple-fpga-bus bindings document). + 3. A FPGA manager driver supporting writing the FPGA. + 4. FPGA bridge drivers. + +The DT overlay includes bindings (documented in bindings/simple-fpga-bus.txt) +that specify: + * Which FPGA manager to use. + * Which image file to load. + * Flags indicating whether this this image is for full reconfiguration or + partial. + * A list of FPGA bridges. + * Child nodes specifying the devices that will be added with appropriate + compatible strings, etc. + +Since this code uses the firmware interface to get the image and DT overlay, +they currently have to be files on the file system. It doesn't have to be that +way forever as DT bindings could be added to point to other sources for the +image. -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/