Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755426AbbKCRSj (ORCPT ); Tue, 3 Nov 2015 12:18:39 -0500 Received: from mail-bl2on0061.outbound.protection.outlook.com ([65.55.169.61]:11379 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1754687AbbKCRSQ (ORCPT ); Tue, 3 Nov 2015 12:18:16 -0500 Authentication-Results: spf=fail (sender IP is 66.35.236.236) smtp.mailfrom=opensource.altera.com; lwn.net; dkim=none (message not signed) header.d=none;lwn.net; dmarc=none action=none header.from=opensource.altera.com; Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=atull@opensource.altera.com; From: To: Rob Herring CC: Moritz Fischer , Josh Cartwright , , , , Pawel Moll , Mark Rutland , "Ian Campbell" , Kumar Gala , Jonathan Corbet , , , , , , , Alan Tull Subject: [PATCH v13 2/6] fpga: add bindings document for simple fpga bus Date: Tue, 3 Nov 2015 11:11:00 -0600 Message-ID: <1446570664-10293-3-git-send-email-atull@opensource.altera.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1446570664-10293-1-git-send-email-atull@opensource.altera.com> References: <1446570664-10293-1-git-send-email-atull@opensource.altera.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [64.129.157.38] X-ClientProxiedBy: BY1PR0201CA0009.namprd02.prod.outlook.com (25.160.191.147) To BLUPR03MB1507.namprd03.prod.outlook.com (25.163.81.25) X-Microsoft-Exchange-Diagnostics-untrusted: 1;BLUPR03MB1507;2:NH6FNO7zWwmEOXLzROr3MTJhr4G9kdKfWcnVD1QWd/pFhWgNkDNcCed0RFK5HP4HOEU8SJjUoqHULF6rpcVkSKLz3V7DvXkHzma0AJWCe1E8Zvm5EZCdZW24jqIxpYecTluYxhxwnULfbInuOJOFnWWe1rsOYSw+OQc5yTKnQxA=;3:4kvRrjOtcL1nu0NfsjGuQ4kdUP2QNTDdQzfvYSth8B11qSG9Zj3WUsSIkNHWlbbdcrHLQ3pD32sOw+4Uzl/Mb2qkZXkXPrlbld6cKGcnZnGno1wjBF++Wx4SMKf6j0cG4OpzRORRYevSrZFcKtErzw==;25:0/V/FFTXodHVK6lkxkeqyMOh+cPxaH72+BshjUym2z3ZJoyryJiMcVAe+pJq7MpHZXYhQdGNEpRVOxTNoHSoUv9VbIV9/8s1reXpNG2T/fHqQqp028lzIOp6xylPGYXQP5w4q5u7qJxmgWLCww9Ex/d2GmT7SkEvPOOZl7hPhwxxfL+FLuGAqx9o1IQpDU+M94RRzq2x1u3sNQhs6sUBCfXSIM+vAhPjYwqHJa3SV1IjDZFoDOBWHXoPMebhB62qui3jfDhhJdTD0of7gnDOcw==;20:6EIibNrCwsGmwd0s6ib2luv+OsVKbTj7GQlUbPDANA3M5GtzS62oMrJCKW2qxGoAsEd9qGMhtz7wS0Jjatbno63XSwsMUQxQZOoQGop6TrDNv20zIyf5HUZD7Hk+vvMj0vT76fjW33eLspllOnGEgpmzO/0j4ZcsaqRcwGElz0Y= X-Microsoft-Antispam-Untrusted: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:BLUPR03MB1507; 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Signed-off-by: Alan Tull --- v9: initial version added to this patchset v10: s/fpga/FPGA/g replace DT overlay example with slightly more complicated example move to staging/simple-fpga-bus v11: No change in this patch for v11 of the patch set v12: Moved out of staging. Changed to use FPGA bridges framework instead of resets for bridges. v13: bridge@0xff20000 -> bridge@ff200000, etc Leave out directly talking about overlays Remove regs and clocks directly under simple-fpga-bus in example Use common "firmware-name" binding instead of "fpga-firmware" --- .../devicetree/bindings/fpga/simple-fpga-bus.txt | 74 ++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt diff --git a/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt b/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt new file mode 100644 index 0000000..9646c09 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/simple-fpga-bus.txt @@ -0,0 +1,74 @@ +Simple FPGA Bus +=============== + +A Simple FPGA Bus is a bus that handles configuring an FPGA and its bridges +before populating the devices below its node. + +Required properties: +- compatible : should contain "simple-fpga-bus" +- #address-cells, #size-cells, ranges: must be present to handle address space + mapping for children. + +Optional properties: +- fpga-mgr : should contain a phandle to a FPGA manager. +- fpga-firmware : should contain the name of a FPGA image file located on the + firmware search path. +- partial-reconfig : boolean property should be defined if partial + reconfiguration of the FPGA is to be done, otherwise full reconfiguration + is done. +- fpga-bridges : should contain a list of bridges that the bus will disable + before programming the FPGA and then enable after the FPGA has been + programmed. + +Example: + +/dts-v1/; +/plugin/; +/ { + fragment@0 { + target-path="/soc"; + __overlay__ { + #address-cells = <1>; + #size-cells = <1>; + + bridge@ff200000 { + compatible = "simple-fpga-bus"; + + #address-cells = <0x2>; + #size-cells = <0x1>; + + ranges = <0x00000000 0x00000000 0xc0000000 0x00010000>, + <0x00000001 0x00020000 0xff220000 0x00000008>, + <0x00000001 0x00010040 0xff210040 0x00000020>; + + fpga-mgr = <&hps_0_fpgamgr>; + firmware-name = "soc_system.rbf"; + + fpga-bridges = <&hps_fpgabridge0>, <&hps_fpgabridge1>, <&hps_fpgabridge2>; + + onchip_memory2_0: memory@000000000 { + device_type = "memory"; + compatible = "ALTR,onchipmem-15.1"; + reg = <0x00000000 0x00000000 0x00010000>; + }; + + jtag_uart: serial@100020000 { + compatible = "altr,juart-15.1", "altr,juart-1.0"; + reg = <0x00000001 0x00020000 0x00000008>; + interrupt-parent = <&intc>; + interrupts = <0 42 4>; + }; + + led_pio: gpio@100010040 { + compatible = "altr,pio-15.1", "altr,pio-1.0"; + reg = <0x00000001 0x00010040 0x00000020>; + altr,gpio-bank-width = <4>; + resetvalue = <0>; + #gpio-cells = <2>; + gpio-controller; + }; + }; + }; + }; +}; + -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/