From: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
To: <tglx@linutronix.de>, <mingo@redhat.com>, <hpa@zytor.com>, <bp@suse.de>
CC: <x86@kernel.org>, <sudeep.holla@arm.com>, <akpm@linux-foundation.org>,
        <geliangtang@163.com>, <tj@kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH V2] x86/AMD: Fix LLC topology for AMD Fam17h systems
Date: Tue, 3 Nov 2015 14:34:59 -0600
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On AMD Fam17h systems, the last level cache is not resident in
Northbridge. Therefore, we cannot assign cpu_llc_id to same
value as Node ID (as we have been doing currently)

We should rather look at the ApicID bits of the core to provide
us the last level cache ID info. Doing that here.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
Changes in V2:
 - Move LLC calculation logic to amd_detect_cmp() and change patch
   header as a result. (This in turn fixes the issue found by
   kbuild bot on the V1 patch)
   
 arch/x86/kernel/cpu/amd.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 4a70fc6..dab371e 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -352,6 +352,8 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 #ifdef CONFIG_SMP
 	unsigned bits;
 	int cpu = smp_processor_id();
+	unsigned int apicid = c->apicid;
+	unsigned int socket_id, core_complex_id;
 
 	bits = c->x86_coreid_bits;
 	/* Low order bits define the core id (index of core in socket) */
@@ -361,6 +363,17 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c)
 	/* use socket ID also for last level cache */
 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 	amd_get_topology(c);
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id = (apicid >> bits) - 1;
+	core_complex_id = (apicid & ((1 << bits) - 1)) >> 3;
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 #endif
 }
 
-- 
2.6.1

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