Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756139AbbKCXv5 (ORCPT ); Tue, 3 Nov 2015 18:51:57 -0500 Received: from d.mail.sonic.net ([64.142.111.50]:54116 "EHLO d.mail.sonic.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752748AbbKCXv4 convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2015 18:51:56 -0500 X-Greylist: delayed 519 seconds by postgrey-1.27 at vger.kernel.org; Tue, 03 Nov 2015 18:51:56 EST Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 8.2 \(2104\)) Subject: Re: [GIT PULL] parisc architecture updates for v4.3 From: Guy Harris In-Reply-To: Date: Tue, 3 Nov 2015 15:51:48 -0800 Cc: Linus Torvalds , David Miller , Linux Kernel Mailing List , Parisc List , James Bottomley , John David Anglin , Network Development Content-Transfer-Encoding: 8BIT Message-Id: <497048AC-407D-4694-A9EF-0E57D014D236@alum.mit.edu> References: <20151025114934.GA11108@ls3530.box> <56393D46.6060903@gmx.de> To: Helge Deller X-Mailer: Apple Mail (2.2104) X-Sonic-CAuth: UmFuZG9tSVbFbe5KJFzYLIP6n26wLt23A06mD+Slw33l4rdnJN3o6tmeTG/h9gfveQd1NaQY98sfnwjWHG27VBMAF4nPNrMv X-Sonic-ID: C;BnDp2IWC5RG3quK7sH9FTg== M;NrE22YWC5RG3quK7sH9FTg== X-Spam-Flag: No X-Sonic-Spam-Details: 0.0/5.0 by cerberusd Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1602 Lines: 27 On Nov 3, 2015, at 3:43 PM, Guy Harris wrote: > To which particular PA-RISC processor are you referring? It might not be the same on all processors. Chapter 3 "Addressing and Access Control" of PA-RISC 2.0 Architecture: http://h21007.www2.hp.com/portal/download/files/unprot/parisc20/PA_3_addressing.pdf says A consistent software view of cache operation requires that implementations never write a clean cache line back to memory. (A cache line can be 16, 32, or 64 bytes in length.) Clean means “not stored into” as opposed to “not changed”. Dirty means “stored into”. A cache line which was stored into in such a way that it was unchanged is considered to be dirty. so, architecturally, it can be 16, 32, or 64 bytes. I'm not sure what When Linux says 'line size' it generally means the cache ownership line size: the minimum block the inter cpu coherence operates on. Most of the architectural evidence for PA systems suggests that this is 16 from the mail message cited means when it speaks of architectural evidence; is that line size different from the line size in the PA-RISC 2.0 Architecture manual? That line size presumably isn't the burst size: 128 seems to be the cache burst fill size (the number of bytes that will be pulled into the cache by a usual operation touching any byte in the area).-- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/