Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755834AbbKDL5t (ORCPT ); Wed, 4 Nov 2015 06:57:49 -0500 Received: from terminus.zytor.com ([198.137.202.10]:39804 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751016AbbKDL5s (ORCPT ); Wed, 4 Nov 2015 06:57:48 -0500 Date: Wed, 4 Nov 2015 03:57:30 -0800 From: tip-bot for Aravind Gopalakrishnan Message-ID: Cc: luto@kernel.org, akpm@linux-foundation.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, Aravind.Gopalakrishnan@amd.com, mingo@kernel.org, bp@suse.de, jacob.w.shin@gmail.com, ray.huang@amd.com, hpa@zytor.com, fweisbec@gmail.com Reply-To: hpa@zytor.com, jacob.w.shin@gmail.com, ray.huang@amd.com, fweisbec@gmail.com, Aravind.Gopalakrishnan@amd.com, linux-kernel@vger.kernel.org, akpm@linux-foundation.org, tglx@linutronix.de, luto@kernel.org, mingo@kernel.org, bp@suse.de In-Reply-To: <1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com> References: <1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/urgent] x86/AMD: Fix last level cache topology for AMD Fam17h systems Git-Commit-ID: e5e84a26ef2909964d964224b805236293fb4c63 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2513 Lines: 67 Commit-ID: e5e84a26ef2909964d964224b805236293fb4c63 Gitweb: http://git.kernel.org/tip/e5e84a26ef2909964d964224b805236293fb4c63 Author: Aravind Gopalakrishnan AuthorDate: Wed, 4 Nov 2015 12:49:42 +0100 Committer: Thomas Gleixner CommitDate: Wed, 4 Nov 2015 12:52:06 +0100 x86/AMD: Fix last level cache topology for AMD Fam17h systems On AMD Fam17h systems, the last level cache is not resident in the northbridge. Therefore, we cannot assign cpu_llc_id to the same value as Node ID as we have been doing until now. We should rather look at the ApicID bits of the core to provide us the last level cache ID info. Signed-off-by: Aravind Gopalakrishnan Cc: Andrew Morton Cc: Andy Lutomirski Cc: Frederic Weisbecker Cc: "H. Peter Anvin" Cc: Huang Rui Cc: Ingo Molnar Cc: Jacob Shin Link: http://lkml.kernel.org/r/1446582899-9378-1-git-send-email-Aravind.Gopalakrishnan@amd.com Signed-off-by: Borislav Petkov Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/amd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 4a70fc6..a8816b3 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -352,6 +352,7 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) #ifdef CONFIG_SMP unsigned bits; int cpu = smp_processor_id(); + unsigned int socket_id, core_complex_id; bits = c->x86_coreid_bits; /* Low order bits define the core id (index of core in socket) */ @@ -361,6 +362,18 @@ static void amd_detect_cmp(struct cpuinfo_x86 *c) /* use socket ID also for last level cache */ per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; amd_get_topology(c); + + /* + * Fix percpu cpu_llc_id here as LLC topology is different + * for Fam17h systems. + */ + if (c->x86 != 0x17 || !cpuid_edx(0x80000006)) + return; + + socket_id = (c->apicid >> bits) - 1; + core_complex_id = (c->apicid & ((1 << bits) - 1)) >> 3; + + per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id; #endif } -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/