Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965527AbbKDOsr (ORCPT ); Wed, 4 Nov 2015 09:48:47 -0500 Received: from relmlor4.renesas.com ([210.160.252.174]:17129 "EHLO relmlie3.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932428AbbKDOsq (ORCPT ); Wed, 4 Nov 2015 09:48:46 -0500 X-IronPort-AV: E=Sophos;i="5.20,243,1444662000"; d="scan'208";a="199058191" From: Phil Edworthy To: "Liviu.Dudau@arm.com" CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Bjorn Helgaas , Arnd Bergmann , Lorenzo Pieralisi , Magnus Subject: RE: PCIe host controller behind IOMMU on ARM Thread-Topic: PCIe host controller behind IOMMU on ARM Thread-Index: AdEXBXpsqoonZ+nqRTu1yvYRg99bGAABv/qAAAApWPA= Date: Wed, 4 Nov 2015 14:48:38 +0000 Message-ID: References: <20151104142412.GS963@e106497-lin.cambridge.arm.com> In-Reply-To: <20151104142412.GS963@e106497-lin.cambridge.arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=phil.edworthy@renesas.com; x-originating-ip: [193.141.220.21] x-microsoft-exchange-diagnostics: 1;PS1PR06MB1178;5:Vf5ly4wZUUCnv5YMp6sACe7MdphYgoiqJ3Ik8HzePNmS1b6++G2fLr+CEjhz4Ugw0D+jTKWlqoYyNsF696BB/COSZK1+EY3Go6mjiMvV5OEEpNqk4kQXh6XC7i5bfPka9A2jEgdaDtK1j+3R1ZvOKg==;24:bzjpek8OHEJy8dmX+HM13tUWfSpyDzAztZqHSoNMBm3JjjS5M+NXmCw9OTUCLub232jOax4+sOZzhogrAQehcEacmHivxAU7OQWwEqT5Fx8=;20:Xez33wG56bTibcKeNuo83ghyDKkPFyW7rGeOU5PeZx0TrYVP4KwgRPJlgKUqBsVgZkNnYaIS3UIoi08Xsn6O3338KUmmrBgrnxXFiKzGxnZnpAVwuCyAKZ+g2IEmjGLVvY95yoNHlNNoYcOT3DdNP8TK+Ci0Udjn3q1Xyp2zork= x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:PS1PR06MB1178; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:; x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(601004)(2401047)(520078)(8121501046)(5005006)(10201501046)(3002001);SRVR:PS1PR06MB1178;BCL:0;PCL:0;RULEID:;SRVR:PS1PR06MB1178; x-forefront-prvs: 0750463DC9 x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(6009001)(189002)(199003)(24454002)(92566002)(11100500001)(2900100001)(76176999)(10400500002)(50986999)(66066001)(76576001)(101416001)(5001960100002)(110136002)(5002640100001)(105586002)(189998001)(40100003)(106356001)(19580395003)(74316001)(97736004)(2351001)(5007970100001)(77096005)(54356999)(87936001)(5003600100002)(81156007)(5004730100002)(122556002)(33656002)(2501003)(86362001)(5008740100001)(2950100001)(102836002)(5890100001);DIR:OUT;SFP:1102;SCL:1;SRVR:PS1PR06MB1178;H:PS1PR06MB1180.apcprd06.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;MX:1;A:1;LANG:en; spamdiagnosticoutput: 1:23 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-originalarrivaltime: 04 Nov 2015 14:48:38.5015 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: PS1PR06MB1178 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by mail.home.local id tA4Emqs5013775 Content-Length: 1932 Lines: 45 Hi Liviu, On 04 November 2015 14:24, Liviu wrote: > On Wed, Nov 04, 2015 at 01:57:48PM +0000, Phil Edworthy wrote: > > Hi, > > > > I am trying to hook up a PCIe host controller that sits behind an IOMMU, > > but having some problems. > > > > I'm using the pcie-rcar PCIe host controller and it works fine without > > the IOMMU, and I can attach the IOMMU to the controller such that any calls > > to dma_alloc_coherent made by the controller driver uses the iommu_ops > > version of dma_ops. > > > > However, I can't see how to make the endpoints to utilise the dma_ops that > > the controller uses. Shouldn't the endpoints inherit the dma_ops from the > > controller? > > No, not directly. > > > Any pointers for this? > > You need to understand the process through which a driver for endpoint get > an address to be passed down to the device. Have a look at > Documentation/DMA-API-HOWTO.txt, there is a nice explanation there. > (Hint: EP driver needs to call dma_map_single). > > Also, you need to make sure that the bus address that ends up being set into > the endpoint gets translated correctly by the host controller into an address > that the IOMMU can then translate into physical address. Sure, though since this is bog standard Intel PCIe ethernet card which works fine when the IOMMU is effectively unused, I don’t think there is a problem with that. The driver for the PCIe controller sets up the IOMMU mapping ok when I do a test call to dma_alloc_coherent() in the controller's driver. i.e. when I do this, it ends up in arm_iommu_alloc_attrs(), which calls __iommu_alloc_buffer() and __alloc_iova(). When an endpoint driver allocates and maps a dma coherent buffer it also needs to end up in arm_iommu_alloc_attrs(), but it doesn't. Thanks Phil ????{.n?+???????+%?????ݶ??w??{.n?+????{??G?????{ay?ʇڙ?,j??f???h?????????z_??(?階?ݢj"???m??????G????????????&???~???iO???z??v?^?m???? ????????I?