Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S965438AbbKDTd1 (ORCPT ); Wed, 4 Nov 2015 14:33:27 -0500 Received: from mail-ob0-f174.google.com ([209.85.214.174]:35513 "EHLO mail-ob0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S965309AbbKDTdZ (ORCPT ); Wed, 4 Nov 2015 14:33:25 -0500 MIME-Version: 1.0 In-Reply-To: References: From: Jean-Michel Hautbois Date: Wed, 4 Nov 2015 20:33:04 +0100 Message-ID: Subject: Re: i.MX6: Increasing VPU frequency To: Jon Nettleton Cc: linux-kernel , linux-clk@vger.kernel.org, linux-arm-kernel , sboyd@codeaurora.org, Michael Turquette , Sascha Hauer , Shawn Guo , Fabio Estevam , Philipp Zabel Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 2103 Lines: 49 2015-11-04 18:04 GMT+01:00 Jon Nettleton : > On Wed, Nov 4, 2015 at 5:52 PM, Jean-Michel Hautbois > wrote: >> Hi ! >> >> I can see in FSL kernel that VPU is configurable to 352M (it defaults >> at 264MHz in mainline I think). >> In the TRM, it is even specified at 352MHz as a default frequency, >> with a maximum of 540MHz. >> >> Would it be possible to allow this clock rating modification if, for >> instance, we select a performance governor in cpufreq, or if a coda >> encoder is started with 1080p for instance ? >> If so, then how is it doable properly ? > > For some reason the FSL kernel configures the VPU to run at 352Mhz in > a very odd way that requires limiting the min cpu-frequency to 792Mhz. > It also requires clocking down a bunch of devices on pll2_pfd2_396m to > 352Mhz. > > The simple solution to this is to instead parent the VPU to > pll2_pfd0_352m which is unused. I have found by default it is stable > decoding but unstable encoding at 352Mhz, most likely due to the > voltage changes needed that limiting the min cpu-freq to 792Mhz > provides. However everything seems to work quite reliably clocking > that pfd to 327Mhz, which still gives a boost of almost 24% > > In my testing the performance gain in then going from 327 to 352 is > minimal. Generally I think you hit AXI bus limitations rather than > VPU performance. Interesting. So you propose to add something like the following in drivers/clk/imx/clk-imx6q.cdrivers/clk/imx/clk-imx6q.c : imx_clk_set_rate(clk[IMX6QDL_CLK_PLL2_PFD0_352M], 327000000); imx_clk_set_parent(clk[IMX6QDL_CLK_VPU_AXI_SEL], clk[IMX6QDL_CLK_PLL2_PFD0_352M]); This should end up with a fastest VPU (in fact ~25% boost is good). Is it the correct way to do it ? Should it be done in coda instead ? And only when needed ? Thanks, JM -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/