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From: Pavel Fedin <p.fedin@samsung.com>
To: "'Krzysztof Kozlowski'" <k.kozlowski@samsung.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
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Cc: "'Rob Herring'" <robh+dt@kernel.org>, "'Pawel Moll'" <pawel.moll@arm.com>,
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References: <cover.1446724046.git.p.fedin@samsung.com>
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In-reply-to: <563BEE44.4040207@samsung.com>
Subject: RE: [PATCH v6 1/4] Documentation: dt-bindings: Describe SROMc
 configuration
Date: Fri, 06 Nov 2015 11:14:49 +0300
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 Hello!

> > +- samsung,srom-timing : array of 6 integers, specifying bank timings in the
> > +                        following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
> > +                        Each value is specified in cycles and has the following
> > +                        meaning and valid range:
> > +                        Tacp : Page mode access cycle at Page mode (0 - 15)
> > +                        Tcah : Address holding time after CSn (0 - 15)
> > +                        Tcoh : Chip selection hold on OEn (0 - 15)
> > +                        Tacc : Access cycle (0 - 32)
> 
> All of the manuals have error here. Probably it can be either: 1-32 or
> 0-31. I would bet on 0-31, what do you think?

 Damn, everything starts from 0, so i automatically put '0 - 32'. The actual time, however, varies from 1 to 32, but the value is
from 0 to 31, i. e. <time> - 1
 What shall we do? Just document this, or adjust the code to take number of cycles and subtract 1? To tell the truth, i'm already
sick of these small fixups, and i would prefer just to fix documentation.

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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