Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752699AbbKGL0z (ORCPT ); Sat, 7 Nov 2015 06:26:55 -0500 Received: from www.linutronix.de ([62.245.132.108]:35126 "EHLO Galois.linutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751592AbbKGL0y (ORCPT ); Sat, 7 Nov 2015 06:26:54 -0500 Date: Sat, 7 Nov 2015 12:26:10 +0100 (CET) From: Thomas Gleixner To: Noam Camus cc: linux-snps-arc@lists.infradead.org, linux-kernel@vger.kernel.org, talz@ezchip.com, gilf@ezchip.com, cmetcalf@ezchip.com, Daniel Lezcano , Rob Herring , John Stultz Subject: Re: [PATCH v2 03/19] clocksource: Add NPS400 timers driver In-Reply-To: <1446893557-29748-4-git-send-email-noamc@ezchip.com> Message-ID: References: <1446297327-16298-1-git-send-email-noamc@ezchip.com> <1446893557-29748-4-git-send-email-noamc@ezchip.com> User-Agent: Alpine 2.11 (DEB 23 2013-08-11) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Linutronix-Spam-Score: -1.0 X-Linutronix-Spam-Level: - X-Linutronix-Spam-Status: No , -1.0 points, 5.0 required, ALL_TRUSTED=-1,SHORTCIRCUIT=-0.0001 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1523 Lines: 46 On Sat, 7 Nov 2015, Noam Camus wrote: > +/* > + * To get the value from the Global Timer Counter register proceed as follows: > + * 1. Read the upper 32-bit timer counter register > + * 2. Read the lower 32-bit timer counter register > + * 3. Read the upper 32-bit timer counter register again. If the value is > + * different to the 32-bit upper value read previously, go back to step 2. > + * Otherwise the 64-bit timer counter value is correct. > + */ > +static cycle_t nps_clksrc_read(struct clocksource *clksrc) > +{ > + u64 counter; > + u32 lower, upper, old_upper; > + void *lower_p, *upper_p; > + int cluster = (smp_processor_id() >> NPS_CLUSTER_OFFSET); > + > + lower_p = nps_msu_reg_low_addr[cluster]; > + upper_p = lower_p + 4; > + > + upper = ioread32be(upper_p); > + do { > + old_upper = upper; > + lower = ioread32be(lower_p); > + upper = ioread32be(upper_p); > + } while (upper != old_upper); > + > + counter = (upper << 32) | lower; > + return (cycle_t)counter; So that clocksource goes up to 1GHz. That means u32 fits ~4.29 seconds. Unless you are striving for NOHZ idle sleep times above that there is no point in doing that 64bit dance. The timekeeping code is perfectly fine with a 32bit value. You just have to set the proper mask. Thanks, tglx -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/